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参数资料
| 型号： | DS4302Z-020+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/8页 |
| 文件大小： | 0K |
| 描述： | IC DAC 5-BIT SGL 0-2.0V 8-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 10µs |
| 位数： | 5 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement (ACK): An Acknowledgement
(ACK) is always the 9th bit transmitted during a byte
transfer. The device receiving data (the master during a
read or the slave during a write operation) performs an
ACK by transmitting a zero during the 9th bit. For tim-
ing, see Figure 3. An ACK is the acknowledgement that
the device is properly receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK from the
master to the slave. The 8 bits of information that are
transferred (most significant bit first) from the slave to
the master are read by the master using the bit read
definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must ACK the last byte read to termi-
nated communication so the slave returns control of
SDA to the master.
Slave Address and the R/W Bit: Each slave on the
2-wire bus responds to a slave addressing byte sent
immediately following a START condition. The slave
address byte contains the slave address and the R/W
bit. The slave address (see Figure 4) is the most signifi-
cant 7 bits and the R/W bit is the least significant bit.
The DS4302’s slave address is 0101100X (binary),
where X is the R/W bit. If the R/W bit is zero
(01011000), the master will write data to the slave. If the
R/W is a one (01011001), the master will read data from
the slave.
Memory Address: During a 2-wire write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is the second byte transmitted
during a write or read operation following the slave
address byte (R/W=0). For a write operation, the mem-
ory address is 10101010 (AAh) and for a read opera-
tion, the memory address is 00000000 (00h).
DS4302
2-Wire, 5-Bit DAC with Three Digital Outputs
_____________________________________________________________________
7
7-BIT SLAVE ADDRESS
MOST
SIGNIFICANT
BIT
DETERMINES
READ OR WRITE
R/W
0
1
0
1
0
Figure 4. Slave Address and the R/W Bit
Figure 3. 2-Wire Timing Diagram
SDA
SCL
STOP
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
START
tBUF
tLOW
tR
tF
tSU:DAT
tSU:STA
tHD:STA
tSU:STO
tSP
REPEATED
START
tHD:STA
tHD:DAT
tHIGH
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS4303 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Voltage Sample and Infinite Hold |
| DS4303K | 功能描述:电源管理IC开发工具 RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| DS4303R/R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Voltage Sample and Infinite Hold |
| DS4303R/T | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Voltage Sample and Infinite Hold |
| DS4303R/T&R | 制造商:Maxim Integrated Products 功能描述:NV ADJ VOLTAGE REFERENCE SOT23-5 - Tape and Reel |
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