参数资料
型号: DS4303R+T&R
厂商: Maxim Integrated Products
文件页数: 6/8页
文件大小: 0K
描述: IC VREF SERIES ADJ SOT-23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
基准类型: 系列,可调式
输出电压: 0.3 V ~ 3.3 V
容差: ±0.03%
温度系数: 62ppm/°C
输入电压: 2.4 V ~ 3.6 V
通道数: 1
电流 - 静态: 1.6mA
电流 - 输出: 1mA(最小值)
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
Electronically Programmable
Voltage Reference
Pin Description
Detailed Description
The DS4303 provides a precise, NV output voltage,
PIN
1
2
3
4
5
NAME
ADJ
GND
V IN
V OUT
V CC
FUNCTION
Adjust Control Input
Ground
Sample Voltage Input
Voltage Output
Power-Supply Voltage
V OUT , making it an ideal solution for factory calibration
of embedded systems. The DS4303 output voltage can
be adjusted over almost the entire operating supply
range of the device, and it can be precisely set to with-
in ±1mV. A graphical description of the DS4303 is pro-
vided in the block diagram.
During factory calibration, a simple adjustment proce-
dure must be followed. This entire procedure includes
setting V IN , toggling ADJ , waiting as V OUT self-adjusts,
V CC
Block Diagram
and waiting for the completion of the EEPROM storage
cycle (See the timing diagram in Figure 1). At the start
of calibration, a voltage must be placed on V IN . This
voltage needs to be completely stable before the
adjustment procedure begins, and it must remain sta-
ble throughout the entire adjustment procedure. The
ADJ
V IN
V CC
R PU
V CC
R PD
ADC
AND
CONTROL
DS4303
12-BIT
DAC
V REF
V OUT
DS4303 will start its self-adjust procedure when the
ADJ pin is pulled low and held low for at least t ADJ ,
after which it can be released at any time. Once ADJ
has been released, it should not be toggled again for
the remainder of the adjustment procedure. After the
falling edge on ADJ and the wait time, t ADJ , the V OUT
self-adjust period begins. The length of the V OUT self-
GND
V OUT
V IN
ADJ
EEPROM
? V OUT x t ST
? V OUT
t W
? V OUT
adjust period can be determined using the formula
? V x t ST , where ? V is | V OUT OLD - V OUT NEW |.
? V OUT x t ST
t W
t ADJ
Figure 1. Timing Diagram
FIRST PROGRAMMING CYCLE
t ADJ
t ADJ
ADDITIONAL PROGRAMMING CYCLES (IF REQUIRED)
6
_____________________________________________________________________
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相关代理商/技术参数
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