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参数资料
| 型号： | DS4M133P+33 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC OSC CLOCK 133.33MHZ 10-LCCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 34 |
| 类型： | 时钟振荡器 |
| 频率： | 133.33MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 74mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-LCCC 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-LCCC |
| 安装类型： | 表面贴装 |
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input-Voltage Low (OE)
VIL
(Note 5)
0
0.3 x
VCC
V
Input-Leakage High (OE)
ILEAKH
OE voltage = VCC
-5
+5
μA
Input-Leakage Low (OE)
ILEAKL
OE voltage = GND
-20
-50
μA
Input-Leakage High (MS)
ILEAKH
MS voltage = VCC
20
50
μA
Input-Leakage Low (MS)
ILEAKL
MS voltage = GND
-5
+5
μA
Input Voltage: High Level (MS)
VIH
(Note 5)
0.75 x
VCC +
0.15V
VCC
V
Input Voltage: Mid Level (MS)
VIM
(Note 5)
0.25 x
VCC +
0.15V
0.75 x
VCC -
0.15V
V
Input Voltage: Low Level (MS)
VIL
(Note 5)
0
0.25 x
VCC -
0.15V
V
LVDS
Output High Voltage
VOH
100
differential load (Notes 2, 5)
1.475
V
Output Low Voltage
VOL
100
differential load (Notes 2, 5)
0.925
V
Differential Output Voltage
|VOD|
100
differential load
250
425
mV
Change in VOD for
Complementary States
|VOD|
100
differential load
25
mV
Offset Output Voltage
VOS
100
differential load (Note 2)
1.125
1.275
V
Change in VOS for
Complementary States
|VOS|
100
differential load
150
mV
Differential Output Impedance
ROLVDS
80
140
LVSSLVDSO
OUTN or OUTP shorted to ground and
measure the current in the shorting path
40
Output Current
LLVDSO
OUTN and OUTP shorted together and
measure the change in ICC
6.5
mA
Output Rise Time (Differential)
tRLVDSO
20% to 80%
175
ps
Output Fall Time (Differential)
tFLVDSO
80% to 20%
175
ps
Duty Cycle
DCYCLE_LVDS
45
55
%
Propagation Delay from OE Going
LOW to Logical 1 at OUTP
tPA1
(Figure 2)
200
ns
Propagation Delay from OE Going
HIGH to Output Active
tP1A
(Figure 2)
200
ns
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