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参数资料
| 型号： | DS4M200D+33 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/7页 |
| 文件大小： | 0K |
| 描述： | IC OSC CLOCK 200MHZ 10-LCCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 27 |
| 类型： | 时钟振荡器 |
| 频率： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 74mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-LCCC 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-LCCC |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 1433 (CN2011-ZH PDF) |
DS4M125/DS4M133/DS4M200
Detailed Description
The DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100k
Ω
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of VCC - 2.0V, while the LVDS
outputs are a logical one. The OE pin has an internal
100k
Ω pullup resistor. When the pin is left floating, the
device output is active.
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
6
_______________________________________________________________________________________
DIVP
DIVFB
X1
X2
THREE-
STATE
PHASE
DET
FILTER
LC-VCO
THREE-
LEVEL
DECODER
DIVOUT
OUTSELN
FREQUENCY SELECTION
OUTDRV
VCC
OE
OUTP
OUTN
MS
GND
DS4M125/
DS4M133/
DS4M200
Figure 1. Functional Diagram
OE
OUTP
tP1A
tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
OE
OUTP
PECL_BIAS
OUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS4M200P+33 | 功能描述:标准时钟振荡器 3.3V Margining Clock w/LVPECL/LVDS Output RoHS:否 制造商:AVX 产品:Standard Clock Oscillators 封装 / 箱体:7 mm x 5 mm 频率:75 MHz 频率稳定性:50 PPM 电源电压:2.5 V 负载电容: 端接类型:SMD/SMT 最小工作温度:0 C 最大工作温度:+ 70 C 输出格式:LVDS 尺寸: 封装:Reel 系列: |
| DS4-M-DC12V | 制造商:AROMAT 功能描述: 制造商:Panasonic Electric Works 功能描述: |
| DS4-M-DC5V | 制造商:Panasonic Electric Works 功能描述: |
| DS4-ML2-DC12V | 制造商:Panasonic Electric Works 功能描述: |
| DS4-ML2-DC24V | 制造商:Panasonic Electric Works 功能描述: |
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