参数资料
型号: DS80C310-QCG+
厂商: Maxim Integrated Products
文件页数: 4/22页
文件大小: 0K
描述: IC MCU HI SPEED 25MHZ 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 欠压检测/复位,POR
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
产品目录页面: 703 (CN2011-ZH PDF)
DS80C310
12 of 22
Note 6:
When addressing external memory. This specification applies to the first clock cycle following the transition. On subsequent
cycles following 1 to 0 transitions, the typical current sink capability of Port 0 and Port 2 is approximately 150
A, and the
minimum current sink capability of ALE and
PSEN is approximately 400
A. On subsequent cycles following 0 to 1
transitions, the typical current drive capability of Port 0 and Port 2 is approximately 110
A.
Note 7:
RST = VCC. This condition mimics operation of pins in I/O mode.
Note 8:
During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition
mode.
Note 9:
Current required from external circuit to hold a logic-low level on an I/O pin while the corresponding port latch bit is set to 1.
This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin must also overcome the transition
current.
Note 10:
Ports 1 and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately
2V.
Note 11:
0.45 < VIN <VCC. Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated as an
address bus on the DS80C310. Peak current occurs near the input transition point of the latch, approximately 2V.
Figure 2. Typical ICC vs. Frequency
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