参数资料
型号: DS80C310-QCG/T&R
厂商: Maxim Integrated Products
文件页数: 22/22页
文件大小: 0K
描述: IC MCU HI SPEED 25MHZ 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 欠压检测/复位,POR
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 带卷 (TR)
DS80C310
9 of 22
Table 2. Data Memory Cycle Stretch Values
CKCON.2–CKCON.0
M2
M1
M0
MEMORY
CYCLES
RD OR WR STROBE
WIDTH IN CLOCKS
25MHz STROBE WIDTH
(ns)
0
2
80
0
1
3 (default)
4
160
0
1
0
4
8
320
0
1
5
12
480
1
0
6
16
640
1
0
1
7
20
800
1
0
8
24
960
1
9
28
1120
DUAL DATA POINTER (DPTR)
Data memory block moves can be accelerated using the DS80C310 dual data pointer (DPTR). The
standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These
are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is
located at SFR 84h and 85h and is called DPTR1. The DPTR select bit (DPS) chooses the active pointer
and is located at the LSB of the SFR location 86h. No other bits in register 86h have any effect and are set
to 0. The user switches between data pointers by toggling the LSB of register 86h. The increment (INC)
instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected
DPTR for any activity. Therefore, only one instruction is required to switch from a source to a destination
address. Using the DPTR saves code from needing to save source and destination addresses when doing a
block move. Once loaded, the software simply switches between DPTR0 and 1. The relevant register
locations are as follows.
DPL
82h
Low byte original DPTR
DPH
83h
High byte original DPTR
DPL1
84h
Low byte new DPTR
DPH1
85h
High byte new DPTR
DPS
86h
DPTR Select (lsb)
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control Register (PCON; 87h) invokes the stop mode. Stop mode is the lowest
power state because it turns off all internal clocking. The ICC of a standard stop mode is approximately
1
A (but is specified in the Absolute Maximum Ratings section). The CPU exits stop mode from an
external interrupt or a reset condition. Internally generated interrupts are not useful since they require
clocking activity.
The DS80C310 allows a resume from stop using INT2–INT5, which are edge-triggered interrupts. An
internal crystal counter manages the startup timing. A delay of 65,536 clocks occurs to allow the crystal
time to stabilize. Software must also insert a delay of 100 machine cycles following the exit from stop
mode. This ensures stabilization of internal timing prior to time-critical software tasks such as serial port
operations or bus access to memory-mapped I/O devices.
相关PDF资料
PDF描述
DS80C310-MCG IC MCU HI SPEED 25MHZ 40-DIP
VE-J3Z-IW-B1 CONVERTER MOD DC/DC 2V 40W
VI-23Z-IV-F4 CONVERTER MOD DC/DC 2V 60W
VE-J3Y-IY-B1 CONVERTER MOD DC/DC 3.3V 33W
VI-23Z-IV-F3 CONVERTER MOD DC/DC 2V 60W
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