参数资料
型号: DS80C411-FNY+
厂商: Maxim Integrated Products
文件页数: 101/102页
文件大小: 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 75MHz
连通性: 1 线,CAN,EBI/EMI,以太网,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 64
程序存储器容量: 64KB(64K x 8)
程序存储器类型: ROM
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
98 of 102
Changing the System Clock/Machine Cycle Clock Frequency
The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock
signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to change
from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in the following sequence: 00b =>
10b => 11b. Attempts to switch between invalid states fail, leaving the CD1, CD0 bits unchanged.
The following sequence must be followed when switching to the frequency multiplier as the internal time source.
This sequence can only be performed when the device is in divide-by-4 operation. The steps must be followed in
this order, although it is possible to have other instructions between them. Any deviation from this order causes the
CD1, CD0 bits to remain unchanged. Switching from frequency multiplier to nonmultiplier mode requires no steps
other than the changing of the CD1, CD0 bits.
1) Ensure that the CD1, CD0 bits are set to 10, and the RGMD (EXIF.2) bit = 0.
2) Clear the crystal multiplier enable (CTM) bit.
3) Set the 4X/2X bit to the appropriate state.
4) Set the CTM bit.
5) Poll the CKRDY bit (EXIF.3), waiting until it is set to 1. This takes approximately 65,536 cycles of the external
crystal or clock source.
6) Set CD1, CD0 to 00. The frequency multiplier is engaged on the machine cycle following the write to these bits.
Figure 21. System Clock Control Diagram
Switchback
As an alternative to software changing the CD1 and CD0 clock control bits to exit PMM, the microcontroller
provides hardware alternatives for automatic switchback to standard speed (divide-by-4) operation. When enabled,
the switchback feature allows serial ports and interrupts to automatically switch back from divide-by-1024 (PMM) to
divide-by-4 (standard speed) operation. This feature makes it very convenient to use the PMM in real-time
applications.
The switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled, and PMM is
selected, two possible events can cause an automatic switchback to divide-by-4 mode. First, if an external interrupt
occurs and is acknowledged, the system clock reverts from PMM to divide-by-4 mode. For example, if INT0 is
enabled and the CPU is not servicing a higher priority interrupt, then switchback occurs on INT0. However, if INT0
is not enabled or the CPU is servicing a higher priority interrupt, then activity on INT0 does not cause switchback to
occur.
A switchback can also occur when an enabled UART detects the start bit, indicating the beginning of an incoming
serial character or when the SBUF register is loaded initiating a serial transmission. Note that a serial character’s
start bit does not generate an interrupt. The interrupt occurs only on reception of a complete serial word. The
automatic switchback on detection of a start bit allows hardware to return to divide-by-4 operation (and the correct
baud rate) in time for a proper serial reception or transmission.
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