
DS8102
Dual Delta-Sigma Modulator and Encoder
2
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V, TA = -40°C to +85°C, fCLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDD Relative to DGND.............-0.3V to +4.0V
Voltage Range on VDD Relative to AGND .............-0.3V to +4.0V
Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V
Voltage Range on Any Pin Relative to DGND
Except AN0+, AN0-, and AN1+, AN1- ...............-0.3V to +4.0V
Voltage Range on AN0+, AN0-, AN1+, and AN1-
Relative to AGND ...............................................-4.0V to +4.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
(Note 2)
MAX
UNITS
Supply Voltage
VDD
VRST
3.3
3.6
V
Power-Fail Reset Voltage
VRST
Monitors VDD
2.7
2.8
2.99
V
Active VDD Current
IDD
Normal operation
3.5
5.0
mA
Shutdown (Power-Down) VDD
Current
ISTOP
RST = 0 or VDD < VRST
2
nA
Input Low Voltage
VIL
DGND
0.3 x VDD
V
Input High Voltage
VIH
0.7 x VDD
VDD
V
Output Low Voltage
(CLKIO, MNOUT)
VOL
IOL = 4mA
DGND
0.4
V
Output High Voltage
(CLKIO, MNOUT)
VOH
IOH = -4mA
VDD - 0.4
V
Input/Output Pin Capacitance
CIO
(Note 3)
15
pF
Input Leakage Current (All Inputs)
IL
-100
+100
nA
CLOCK SOURCE
External Clock Input Frequency
fXCLK
CLKSEL = 1
DC
8
MHz
External Clock Input Period
tXCLK-CLCL CLKSEL = 1
125
ns
External Clock Input Duty Cycle
tXCLK-DUTY CLKSEL = 1
40
60
%
Internal Oscillator Output
Frequency
fICLK
CLKSEL = 0
7.5
8.0
8.5
MHz
Internal Oscillator Output Duty
Cycle
tICLK-DUTY
CLKSEL = 0
47.8
49.1
49.7
%
ANALOG-TO-DIGITAL CONVERTER
AFE Warmup Delay
tWU1
fICLK = 8MHz (Notes 1, 4)
1.02
ms
Reference Buffer Warmup Delay
tWU2
fICLK = 8MHz (Notes 1, 5)
7.17
ms
OSR = 32
16
OSR = 64
19
OSR = 128
22
Decimator Output (Note 6)
OSR = 256
24
Bits
Integral Nonlinearity
INL
(Notes 1, 6)
±0.01
%FSR
Offset Error
Gain = 1 (Note 6)
1.4
mV