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参数资料
| 型号： | DS8500-JND+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | IC MODEM HART SGL 3.6V 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 应用： | HART 调制解调器 |
| 接口： | 串行 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 供应商设备封装： | 20-TQFN-EP（5x5） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 703 (CN2011-ZH PDF) |
HART Modem
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Specifications to -40°C are guaranteed by design and are not production tested.
Note 2: Active currents are measured when the device is driven by an external clock XCEN = 1 condition.
Note 3: Guaranteed by design and not production tested.
Note 4: Accuracy is guaranteed based on the external crystal or clock provided.
Voltage Range on All Pins (including AVDD,
DVDD) Relative to Ground .................................-0.5V to +3.6V
Voltage Range on Any Pin Relative to
Ground Except AVDD, DVDD .............-0.5V to (VDVDD + 0.5V)
Operating Temperature Range ...........................-40
°C to +85°C
Storage Temperature Range .............................-65
°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Supply Voltage
VDVDD
2.7
3.6
V
Analog Supply Voltage
VAVDD
VAVDD = VDVDD
2.7
3.6
V
Ground
GND
AGND = DGND
0
V
Digital Power-Fail Reset Voltage
VRST
Monitors VDVDD
2.59
2.64
2.69
V
Active Current
IDD
VAVDD = VDVDD = 2.7V (Note 2)
285
μA
Input Low Voltage
VIL
DGND
0.30 x
VDVDD
V
Input High Voltage
VIL
0.75 x
VDVDD
V
Output Low Voltage
VOL
IOL = 4mA
DGND
0.4
V
Output High Voltage
VOH
IOH = -4mA
0.8 x
VDVDD
V
I/O Pin Capacitance
CIO
Guaranteed by design (Note 3)
15
pF
RST Pullup Resistance
RRST
19
45
k
Input Leakage Current XTAL,
RST
IILRX
-30
+30
μA
Input Leakage Current All Other
Pins
IIL
-2
+2
μA
Input Low Current for
RST
IIL1
VIN = 0.4V
170
μA
CLOCK SOURCE
External Clock Frequency
fHFIN
-1%
3.6864
+1%
MHz
VOLTAGE REFERENCE
Internal Reference Voltage
VREF
1.23
V
FSK INPUT
Input Voltage Range at FSK_IN
0
VREF
V
FSK OUTPUT
Output Voltage at FSK_OUT
VOUT
AC-coupled max 30k
load
400
500
600
mVP-P
For a mark
-1%
1200
+1%
Frequency of FSK_OUT (Note 4)
For a space
-1%
2200
+1%
Hz
DS8500
2
Maxim Integrated
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