参数资料
型号: DS87C520-QCL/T&R
厂商: Maxim Integrated Products
文件页数: 2/43页
文件大小: 0K
描述: IC MCU EPROM/ROM 33MHZ HS 44PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
系列: 87C
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC(J 形引线)
包装: 带卷 (TR)
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
10 of 43
MEMORY RESOURCES
Like the 8051, the DS87C520/DS83C520 use three memory areas. The total memory configuration of the
DS87C520/DS83C520 is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM.
The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is
reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes
of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap
among the 256 bytes and the 1kB as they use different addressing modes and separate instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CERDIP should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the data sheet.
PROGRAM MEMORY ACCESS
On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the
maximum address of on-chip ROM will cause the device to access off-chip memory. However, the
maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can
cause the DS87C520/DS83C520 to behave like a device with less on-chip memory. This is beneficial
when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically
variable. Thus a portion of memory can be removed from the memory map to access off-chip memory,
and then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the
memory map allowing the full 64kB memory space to be addressed from off-chip memory. ROM
addresses that are larger than the selected maximum are automatically fetched from outside the part via
Ports 0 and 2. A depiction of the ROM memory map is shown in Figure 2.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 have the following effect.
RMS2
RMS1
RMS0
MAXIMUM ON-CHIP ROM ADDRESS
0
0kB
0
1
1kB/03FFh
0
1
0
2kB/07FFh
0
1
4kB/0FFFh
1
0
8kB/1FFFh
1
0
1
16kB (default)/3FFFh
1
0
Invalid—reserved
1
Invalid—reserved
The reset default condition is a maximum on-chip ROM address of 16kB. Thus no action is required if
this feature is not used. When accessing external program memory, the first 16kB would be inaccessible.
To select a smaller effective ROM size, software must alter bits RMS2–RMS0. Altering these bits
requires a Timed-Access procedure as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example, assume that the DS87C520/DS83C520 are executing instructions from internal program
memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a
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