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参数资料
| 型号： | DS90CR217MTD/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 21BIT CHAN LINK 48TSSOP |
| 产品培训模块： | Interconnect Solutions for LVDS Applications |
| 标准包装： | 38 |
| 类型： | 发射器 |
| 驱动器/接收器数： | 21/3 |
| 规程： | LVDS |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1280 (CN2011-ZH PDF) |
| 其它名称： | *DS90CR217MTD *DS90CR217MTD/NOPB DS90CR217MTD |
SNLS226A – OCTOBER 2006 – REVISED FEBRUARY 2013
Figure 14. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS
interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example,
a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns. Differential skew (
Δt within
one differential pair), interconnect skew (
Δt of one differential pair to another) and clock jitter will all reduce the
available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input
to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-
to-channel skew and interconnect skew as a part of the overall jitter/skew budget.
COMMON-MODE vs. DIFFERENTIAL MODE NOISE MARGIN
The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100
mV threshold therefore providing approximately 200 mV of differential noise margin. Common-mode protection is
of more importance to the system's operation due to the differential data transmission. LVDS supports an input
voltage range of Ground to +2.4V. This allows for a ±1.0V shifting of the center point due to ground potential
differences and common-mode noise.
TRANSMITTER INPUT CLOCK
The transmitter input clock must always be present when the device is enabled (PWR DWN = HIGH). If the clock
is stopped, the PWR DWN pin must be used to disable the PLL. The PWR DWN pin must be held low until after
the input clock signal has been reapplied. This will ensure a proper device reset and PLL lock to occur.
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and
data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either
device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total
power dissipation for each device will decrease to 5
μW (typical).
The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter
input clock may also be applied after power up; however, the use of the PWR DWN pin is required as described
in the TRANSMITTER INPUT CLOCK section. Do not power up and enable (PWR DWN = HIGH) the transmitter
without a valid clock signal applied to the TxCLK IN pin.
The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs
(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the
receiver inputs are shorted to VCC through an internal diode. Current is limited (5 mA per input) by the fixed
current mode drivers, thus avoiding the potential for latchup when powering the device.
10
Copyright 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR217
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS90CR217MTDX | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| DS90CR217MTDX/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| DS90CR218 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz |
| DS90CR218A | 制造商:NSC 制造商全称:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz |
| DS90CR218A_06 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 12 MHz to 85 MHz |
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