参数资料
型号: DSPIC30F6010-20E/PF
厂商: Microchip Technology
文件页数: 19/110页
文件大小: 0K
描述: IC DSPIC MCU/DSP 144K 80TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 90
系列: dsPIC™ 30F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 20 MIPS
连通性: CAN,I²C,SPI,UART/USART
外围设备: 高级欠压探测/复位,LVD,电机控制 PWM,QEI,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 144KB(48K x 24)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 80-TQFP
包装: 托盘
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名称: DSPIC30F601020EPF
dsPIC30F6010
DS70119E-page 14
2006 Microchip Technology Inc.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The fol-
lowing instructions and data sizes are supported:
1.
DIVF
– 16/16 signed fractional divide
2.
DIV.sd
– 32/16 signed divide
3.
DIV.ud
– 32/16 unsigned divide
4.
DIV.sw
– 16/16 signed divide
5.
DIV.uw
– 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the REPEAT instruction, as shown
in Table 2-1 (REPEAT will execute the target instruction
{operand value+1} times). The REPEAT loop count must
be set up for 18 iterations of the DIV/DIVF instruction.
Thus, a complete divide operation requires 19 cycles.
TABLE 2-1:
DIVIDE INSTRUCTIONS
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inher-
ent
accumulator-to-accumulator
operations,
which
require no additional data. These instructions are ADD,
SUB
and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1.
Fractional or integer DSP multiply (IF).
2.
Signed or unsigned DSP multiply (US).
3.
Conventional or convergent rounding (RND).
4.
Automatic saturation on/off for ACCA (SATA).
5.
Automatic saturation on/off for ACCB (SATB).
6.
Automatic saturation on/off for writes to data
memory (SATDW).
7.
Accumulator
Saturation
mode
selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Note:
The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn
→ W0; Rem → W1
DIV.sd
Signed divide: (Wm + 1:Wm)/Wn
→ W0; Rem → W1
DIV.ud
Unsigned divide: (Wm + 1:Wm)/Wn
→ W0; Rem → W1
DIV.sw
Signed divide: Wm/Wn
→ W0; Rem → W1
DIV.uw
Unsigned divide: Wm/Wn
→ W0; Rem → W1
Note:
For CORCON layout, see Table 3-3.
TABLE 2-2:
DSP INSTRUCTION
SUMMARY
Instruction
Algebraic Operation
CLR
A = 0
ED
A = (x – y)2
EDAC
A = A + (x – y)2
MAC
A = A + (x * y)
MOVSAC
No change in A
MPY
A = x * y
MPY.N
A = – x * y
MSC
A = A – x * y
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