参数资料
型号: DSPIC33FJ12GP201-E/SO
厂商: Microchip Technology
文件页数: 34/90页
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 18SOIC
产品培训模块: Asynchronous Stimulus
标准包装: 42
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 13
程序存储器容量: 12KB(12K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 18-SOIC(0.295",7.50mm 宽)
包装: 管件
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
dsPIC33F
DS70155C-page 2
Preliminary
2005 Microchip Technology Inc.
Timers/Capture/Compare/PWM
Timer/Counters: up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
- 1 timer runs as Real-Time Clock with external
32 kHz oscillator
- Programmable prescaler
Input Capture (up to 8 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
Output Compare (up to 8 channels):
- Single or Dual 16-Bit Compare mode
- 16-Bit Glitchless PWM mode
Communication Modules
3-wire SPI (up to 2 modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
- 8-word FIFO buffers
I2C (up to 2 modules):
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
-Address masking
UART (up to 2 modules):
- Interrupt-on-address bit detect
- Wake-up-on-Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
-IrDA encoding and decoding in hardware
- High-Speed Baud mode
Data Conversion Interface (DCI) module:
- Codec interface
- Supports I2S and AC’97 protocols
- Up to 16-bit data words, up to 16 words per
frame
- 4-word deep TX and RX buffers
Enhanced CAN 2.0B active (up to 2 modules):
- Up to 8 transmit and up to 16 receive buffers
- 16 receive filters and 3 masks
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- FIFO mode using DMA
Motor Control Peripherals
Motor Control PWM (up to 8 channels):
- 4 duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Manual output override control
- Up to 2 Fault inputs
- Trigger for A/D conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/
underflow
Analog-to-Digital Converters
Up to two 10-bit or 12-bit A/D modules in a device
10-bit 2.2 Msps or 12-bit 1 Msps conversion:
- 2 or 4 simultaneous samples
- Up to 32 input channels with auto-scanning
- 16-deep result buffer
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- ±1 LSB max integral nonlinearity
- ±1 LSB max differential nonlinearity
CMOS Flash Technology
Low-power, high-speed Flash technology
Fully static design
3.3V (+/- 10%) operating voltage
Industrial temperature
Low-power consumption
Packaging:
100-pin TQFP (14x14x1 mm and 12x12x1 mm)
80-pin TQFP (12x12x1 mm)
64-pin TQFP (10x10x1 mm)
Note:
See Table 1-1 and Table 1-2 for exact
peripheral features per device.
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