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参数资料
| 型号： | E1110 |
| 英文描述： | E1110 Gigabit Media Access Controller (MAC) |
| 中文描述： | E1110千兆媒体访问控制器（MAC） |
| 文件页数： | 2/2页 |
| 文件大小： | 48K |
| 代理商： | E1110 |
E1110 Gigabit Media Access Controller
The E1110 complements LSI Logic’s existing CoreWare portfolio that
includes E110, CAMs, embedded FPGA, high speed I/Os, ARM, MIPS and
ZSPTM-based cores. By collaborating with LSI Logic, designers can have access
to a variety of verified building blocks to quickly design unique solutions that
provide a competitive edge for today’s marketplace. In addition, LSI Logic is a
total Gigabit Ethernet solutions partner that supports the entire design solution
including application and design support, physical layout, prototyping, and
production manufacturing.
For more information please call:
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800 574 4286
LSI Logic Europe Ltd.
European Headquarters
United Kingdom
Tel: 44 1344 426544
Fax: 44 1344 481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81 3 5463 7165
Fax: 81 3 5463 7820
LSI Logic web site
www.lsilogic.com
CoreWare, G12, the LSI Logic logo, The Communications
Company and ZSP are trademarks or registered
trademarks of LSI Logic Corporation. All other
product and service names used herein may be
trademarks or registered trademarks of their
respective companies.
LSI Logic Corporation reserves the right to make
changes to any products and services herein at any
time without notice. LSI Logic does not assume any
responsibility or liability arising out of the
application or use of any product or service
described herein, except as expressly agreed to in
writing by LSI Logic; nor does the purchase, lease,
or use of a product or service from LSI Logic
convey a license under any patent rights,
copyrights, trademark rights, or any other of the
intellectual property rights of LSI Logic or of third
parties.
Copyright 2001 by LSI Logic Corporation.
All rights reserved.
Order No. C20041
501.1k.SR.IK - Printed in USA
CPU Bus
GMII/MII/TBI
Port 1
GMII/MII/TBI
Port 12
Address
Cache
SDRAM
Controller
TX/RX FIFO
MPU
802.1d
$I
$D
R-File
75 x 72
E1110
10/100/1G MAC
802.3x
R-File
75 x 72
E1110
10/100/1G MAC
802.3x
L2/L3 Switch Fabric
Figure 2. Block Diagram of a 12 Port L2/L3 Switch Using 12 E1110 MACs
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