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参数资料
| 型号： | E28F400BX-B80 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 256K X 16 FLASH 12V PROM, 80 ns, PDSO56 |
| 封装： | 20 X 14 MM, TSOP-56 |
| 文件页数： | 16/50页 |
| 文件大小： | 449K |
| 代理商： | E28F400BX-B80 |
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28F400BX-TB 28F004BX-TB
Similar to erasure
the status register indicates
whether programming is complete While the pro-
gram sequence is executing bit 7 of the status regis-
ter is a ‘‘0’’ The status register can be polled by
toggling either CE
or OE
to determine when the
program sequence is complete
Only the Read
Status Register command is valid while program-
ming is active
When programming is complete the status bits
which indicate whether the program operation was
successful should be checked If the programming
operation was unsuccessful Bit 4 of the status regis-
ter is set to a ‘‘1’’ to indicate a Program Failure If
Bit 3 is set then VPP was not within acceptable limits
and the WSM will not execute the programming se-
quence
The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after programming is completed however it
must be recognized that reads from the memory
status register or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read
Figure 12 shows a system software flowchart for de-
vice byte programming operation Figure 13 shows a
similar flowchart for device word programming oper-
ation (28F400BX-only)
445 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI along with the addresses A 1217
for the
28F400BX or A 1218 for the 28F004BX identifying
the block to be erased These addresses are latched
internally when the Erase Confirm command is is-
sued Block erasure results in all bits within the block
being set to ‘‘1’’
The WSM will execute a sequence of internally
timed events to
1 Program all bits within the block
2 Verify that all bits within the block are sufficiently
programmed
3 Erase all bits within the block and
4 Verify that all bits within the block are sufficiently
erased
While the erase sequence is executing Bit 7 of the
status register is a ‘‘0’’
When the status register indicates that erasure is
complete the status bits which indicate whether the
erase operation was successful should be checked
If the erasure operation was unsuccessful Bit 5 of
the status register is set to a ‘‘1’’ to indicate an
Erase Failure If VPP was not within acceptable limits
after the Erase Confirm command is issued the
WSM will not execute an erase sequence instead
Bits of the status register is set to a ‘‘1’’ to indicate
an Erase Failure and Bit 3 is set to a ‘‘1’’ to identify
that VPP supply voltage was not within acceptable
limits
The status register should be cleared before at-
tempting the next operation Any CUI instruction can
follow after erasure is completed however it must
be recognized that reads from the memory array
status register or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command A Read Array command must first be giv-
en before memory contents can be read
Figure 14 shows a system software flowchart for
Block Erase operation
4451 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete an Erase Suspend command
is provided This allows erase-sequence interruption
in order to read data from another block of the mem-
ory Once the erase sequence is started writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se-
quence at a predetermined point in the erase algo-
rithm The status register must be read to determine
when the erase operation has been suspended
At this point a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended The only other
valid command at this time is the Erase Resume
command or Read Status Register operation
Figure 15 shows a system software flowchart detail-
ing the operation
23
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| E28F400BX-T120 | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
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| E2SAA10-30.000MTR | QUARTZ CRYSTAL RESONATOR, 30 MHz |
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相关代理商/技术参数 |
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|---|---|
| E28F400BX-T120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| E28F400BX-T60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| E28F400BX-T80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| E28F400CVB60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| E28F400CV-B60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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