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参数资料
| 型号： | E629-EDGE629 |
| 英文描述： | 1 GHz Timing Deskew and Quad Fanout Element |
| 中文描述： | 1 GHz的定时偏移校正和四扇出元素 |
| 文件页数： | 13/17页 |
| 文件大小： | 137K |
| 代理商： | E629-EDGE629 |
5
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
TARGET
Edge629
Fine Delay Select
The fine delay section may be selected or bypassed by a
multiplexer (see Figure 2). If SFD (Select Fine Delay) is
high, Fine Delay will be used. If SFD is low, Fine Delay
will be bypassed.
Fine Delay DAC Outputs
DAC_FINE_(0–3) are analog voltage outputs from the on-
board DACs which program the fine delay elements of
each channel.
DAC_FINE_(0-3) pins are for test purposes only. Nothing
should be connected to these pins.
Circuit Description
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Fine Delay
Fine delay is accomplished using an analog delay cell
and an on-chip 6 bit DAC (see Figure 2). The fine delay
range is designed to be ~2X the coarse delay resolution.
Fine delay provides a total delay span of:
LSB 1 Fine LSB
= 2.5 ps (see note)
2 Fine LSB
= 5 ps
4 Fine LSB
= 10 ps
8 Fine LSB
= 20 ps
16 Fine LSB = 40 ps
MSP 32 Fine LSB = 80 ps
0 ns
≤ Fine Delay Range ≤ 157.5 ps.
Note: Because the transfer function is non-linear, some
LSB steps could be as large as 5 ps.
Each channel has its own unique delay setting and may
be programmed independently from all other channels.
The fine delay of any channel will not affect the coarse
delay of that channel, nor will it affect the overall delay
of any other channel.
The propagation delay of a rising and falling edge will
track each other over the entire span of fine delay.
(Adding or subtracting fine delay will not cause pulse
width distortion.)
Figure 2. Fine Delay Architecture
6 Bit DAC
SFD
T
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