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参数资料
| 型号： | EDI2CG472128V12D2 |
| 英文描述： | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，12ns,同步/同步脉冲静态RAM模块) |
| 中文描述： | 4x128Kx72，3.3同步/同步突发静态存储器（4x128Kx72，3.3伏，12ns，同步/同步脉冲静态内存模块） |
| 文件页数： | 1/12页 |
| 文件大小： | 354K |
| 代理商： | EDI2CG472128V12D2 |
EDI2CG472128V
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
The EDI2CG472128VxxD2 is a Synchronous/Synchronous Burst
SRAM, 84 position Dual Key; Double High DIMM (168 contacts)
Module, organized as 4x128Kx72. The Module contains eight (8)
Synchronous Burst Ram Devices, packaged in the industry stan-
dard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/Sync
Burst, Flow-Through, with support for either linear or sequential
burst. This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only Mode,
provides a high performance cost advantage over BiCMOS asyn-
chronous device architectures.
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
FEATURES
s 4x128Kx72 Synchronous, Synchronous Burst
s Access Speed(s): tKHQV = 8.5, 10, 12, 15ns
s Flow-Through Architecture
s Linear and Sequential Burst Support via MODE pin
s Clock Controlled Registered Module Enable (EM\)
s Clock Controlled Registered Bank Enables (E1\, E2\, E3\, E4\)
s Clock Controlled Byte Write Mode Enable (BWE\)
s Clock Controlled Byte Write Enables (BW1-8\)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW\)
s Aysnchronous Output Enable (G\)
s Internally self-timed Write
s Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)
s Gold Lead Finish
s 3.3V
± 10% Operation
s Common Data I/O
s High Capacitance (30pF) drive, at rated Access Speed
s Single total array Clock
s Multiple Vcc and Vss
March 1998 Rev. 0
ECO# 10038
4x128Kx72, 3.3V Sync/Sync Burst SRAM Dual Key DIMM
相关PDF资料 |
PDF描述 |
|---|---|
| EDI2CG472128V15D2 | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，15ns,同步/同步脉冲静态RAM模块) |
| EDI2CG472128V85D2 | 4x128Kx72, 3.3V Sync/Sync Burst SRAM(4x128Kx72, 3.3V，8.5ns,同步/同步脉冲静态RAM模块) |
| EDI2CG472256V10D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，10ns,同步/同步脉冲静态RAM模块(流通结构）) |
| EDI2CG472256V12D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，12ns,同步/同步脉冲静态RAM模块(流通结构）) |
| EDI2CG472256V15D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，15ns,同步/同步脉冲静态RAM模块(流通结构）) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EDI2CG472128V15D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472128V85D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:4 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472128V-D2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SSRAM Modules |
| EDI2CG472256V | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V10D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
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