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参数资料
| 型号： | EDI2CG472256V-D2 |
| 英文描述： | SSRAM Modules |
| 中文描述： | 的SSRAM模块 |
| 文件页数： | 8/11页 |
| 文件大小： | 172K |
| 代理商： | EDI2CG472256V-D2 |
EDI2CG272128V
6
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
FIG. 3 SYNCHRONOUS ONLY READ CYCLE
READ CYCLE TIMING PARAMETERS
*TBD
8.5ns
9ns
12ns
15ns
Description
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time
tKHKH
**10
12
15
ns
Clock High Time
tKHKL
**
4
5
ns
Clock Low Time
tKLKH
**
4
5
ns
Clock to Output Valid
tKHQV
**
9
10
12
ns
Clock to Output Invalid
tKHQX1
**
3
ns
Clock to Output Low-Z
tKHQX
**
2
ns
Output Enable to Output Valid
tGLQV
**
4
5
ns
Output Enable to Output Low-Z
tGLQX
**
0
ns
Output Enable to Output High-Z
tGHQZ
**
4
5
ns
Address Setup
tAVKH
*
2.5
ns
Bank Enable Setup
tEVKH
*
2.5
ns
Address Hold
tKHAX
*
1.0
ns
Bank Enable Hold
tKHEX
*
1.0
ns
First
Second
Third
Fourth
Address
(external)
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A00
A..A11
A..A10
A..A11
A..A00
A..A01
A..A11
A..A10
A..A01
A..A00
BURST ADDRESS TABLE (MODE = VSS)
BURST ADDRESS TABLE (MODE = NC/VCC)
First
Second
Third
Fourth
Address
(external)
(internal)
A..A00
A..A01
A..A10
A..A11
A..A01
A..A10
A..A11
A..A00
A..A10
A..A11
A..A00
A..A01
A..A11
A..A00
A..A01
A..A10
tKHQX
DQ
Read Cycle
Q(Addr 1)
Q(Addr 2)
tKHQZ
GW
G
ADDR
EX
CLK
tKHQV
Addr 1
Addr 2
Addr 1
tKHKH
tKLKH
tKHKL
tGLQX
Back to Back Read
tKHQX1
tGLQV
tKHAX
tAVKH
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相关代理商/技术参数 |
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| EDI2DL32256V | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256Kx32 Synchronous Pipline Burst SRAM 3.3V |
| EDI2DL32256V35BC | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:256Kx32 Synchronous Pipline Burst SRAM 3.3V |
| EDI2DL32256V38BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Fast Synchronous SRAM |
| EDI2DL32256V40BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Fast Synchronous SRAM |
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