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参数资料
| 型号： | EDI88512CA17CC |
| 英文描述： | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R |
| 中文描述： | x8的SRAM |
| 文件页数： | 5/8页 |
| 文件大小： | 152K |
| 代理商： | EDI88512CA17CC |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
tAVQX
tAVQV
tAVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA I/O
READ CYCLE 2 (WE HIGH)
tAVQV
tELQV
tGLQV
tELQX
tSHQV
tSHQX
tGLQX
tAVAV
tEHQZ
tGHQZ
OE
CS2
tSLQZ
CS1
WS32K32-XHX
FIG. 2
TIMING WAVEFORM - READ CYCLE
FIG. 4
WRITE CYCLE2
FIG. 3
WRITE CYCLE 1
ADDRESS
DATA IN
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
tWLEH
tEHAX
tELEH
tDVEH
tEHDX
tAVAV
DATA VALID
WE
CS1
tAVEL
CS2
ADDRESS
DATA IN
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
tAVWH
tELWH
tWHAX
tWLWH
tDVWH
tWLQZ
tWHQX
tAVWL
tWHDX
tAVAV
DATA VALID
HIGH Z
WE
tSHWH
CS1
DATA OUT
CS2
WRITE CYCLE 3
ADDRESS
DATA IN
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
tWLSL
tSLAX
tSHSL
tDVSL
tSLDX
tAVAV
DATA VALID
WE
CS1
tAVSH
CS2
相关PDF资料 |
PDF描述 |
|---|---|
| EDI88512CA17CI | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R |
| EDI88512CA17CM | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 8-MSOP |
| EDI88512CA17F32B | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 8-MSOP T&R |
| EDI88512CA17F32C | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 8-MSOP T&R |
| EDI88512CA17F32I | Dual 12MHz Rail-to-Rail Input-Output Buffer; Temperature Range: -40°C to 85°C; Package: 8-MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EDI88512CA17CI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| EDI88512CA17CM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| EDI88512CA17F32B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| EDI88512CA17F32C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
| EDI88512CA17F32I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SRAM |
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