参数资料
型号: EDI8L32128C
英文描述: 128Kx32 CMOS High Speed SRAM(128Kx32高速CMOS静态RAM)
中文描述: 128Kx32的CMOS高速静态存储器(128Kx32高速的CMOS静态RAM)的
文件页数: 1/5页
文件大小: 87K
代理商: EDI8L32128C
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8L32128C
December 2000 Rev. 5
ECO #13525
128Kx32 CMOS High Speed Static RAM
FEATURES
s 128Kx32 bit CMOS Static
s Random Access Memory Array
Fast Access Times: 12, 15, 17, 20, and 25ns
Individual Byte Enables
User Configurable Organization with Minimal Additional
Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
s Surface Mount Package
68 Lead PLCC, No. 99 (JEDEC MO-47AE)
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise Immunity
s Single +5V (
±5%) Supply Operation
DESCRIPTION
The EDI8L32128C is a high speed, high performance, four megabit
density Static RAM organized as a 128Kx32 bit array.
Four Chip Enables, Write Control, and Output Enable provide the
user with a flexible memory solution. The user may independently
enable each of the four bytes, and, with minimal additional
peripheral logic, the unit may be configured as a 256Kx16 or
512Kx8 array.
Fully asynchronous circuitry is used, requiring no clocks or re-
freshing for operation and providing equal access and cycle times
for ease of use.
The EDI8L32128C, allows 4 megabits of memory to be placed in
less than 0.990 square inches of board space; a savings of 0.885
square inches over four standard 128Kx8 components.
NOTE: Solder Reflow temperature should not exceed 230
°C
NOTE:
Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are word select pins.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
DQ31
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
DQ0
9
DQ16
8N
C
7N
C
6E
3
5E
2
4E
1
3E
0
2N
C
1
VCC
68
NC
67
NC
66
G
65
W
64
A16
63
A15
62
A14
61
DQ15
BLOCK DIAGRAM
A0-16
G
W
E0
E1
E2
E3
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
128K x 32
Memory
Array
17
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
A-16
Address Inputs
E-3
Chip Enables (One per Byte)
W
Master Write Enable
G
Master Output Enable
DQ-31
Common Data Input/Output
VCC
Power (+5V
±5%)
VSS
Ground
NC
No Connection
TOP VIEW
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