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参数资料
| 型号： | EF-ISE-EMBD-NL |
| 厂商： | Xilinx Inc |
| 文件页数： | 23/50页 |
| 文件大小： | 0K |
| 描述： | SOFTWARE ISE EMBD |
| 标准包装： | 1 |
| 系列： | ISE® 设计套件 |
| 类型： | 集成软件环境（ISE） |
| 适用于相关产品： | Xilinx FPGAs |
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ISE Design Suite 13.1
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AXI Video Direct Memory Access v1.0 (AXI4, AXI4-Stream, AXI4-Lite)
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Provides a flexible interface for controlling and synchronizing video frame
stores from external memory. Multiple VDMAs from different clock domains
can be linked together to control frame store reads and writes from multiple
sources.
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Communication DSP Building Blocks
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Linear Algebra Toolkit v1.0 (AXI4-Stream)
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Implements basic Matrix operations - Matrix-Matrix Addition, Subtraction,
Matrix-Scalar Multiplication and Matrix-Matrix Multiplication.
This IP provides flexible and optimized building blocks for developing
complex composite functions for various signal and data processing
applications.
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FPGA Features and Support
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Configures one or more Virtex-7 and Kintex-7 FPGA GTX transceivers either
from scratch, or using industry standard templates, using a custom Verilog or
VHDL wrapper.
Also provides an example design, testbench, and scripts to allow you to
observe the transceivers operating in simulation and in hardware.
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The XADC Wizard generates an HDL wrapper to configure a single 7 Series
FPGA XADC primitive for user-specified channels and alarms.
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Standard Bus Interfaces and I/O
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7-Series Integrated Block for PCI Express (PCIe) v1.0 (AXI4-Stream)
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Implements 1-lane, 2-lane, 4-lane, or 8-lane configurations. The IP uses the 7
Series Integrated Hard IP Block for PCI Express in conjunction with flexible
architectural features to implement a PCI Express Base Specification v2.1
compliant PCI Express Endpoint or Root Port.
Unique features of the LogiCORE IP for PCI Express are the high
performance AXI Interface, optimal buffering for high bandwidth
applications, and BAR checking and filtering.
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Wireless IP
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Triple Rate SDI v1.0 (AXI4-Stream)
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Provides receiver and transmitter interfaces for the SMPTE SD-SDI, HD-SDI,
and 3G-SDI standards.
The Triple-Rate SDI receiver and transmitter are provided as unencrypted
source code in both Verilog and VHDL, allowing you to fully customize these
interfaces as required by your specific applications.
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3GPP LTE PUCCH Receiver v1.0 (AXI4-Stream)
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Provides designers with an LTE Physical Uplink Control Channel Receiver
block for the 3GPP TS 36.211 v9.0.0 Physical Channels and Modulation
(Release 9) specification.
Support for channel estimation, demodulation and decoding.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
23
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EF-ISE-LOG-FL | 功能描述:DESIGN SUITE LOGIC EDITION RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-LOG-NL | 功能描述:DESIGN SUITE LOGIC EDITION ISE12 RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-FL | 功能描述:ISE DESIGN SYST FLOATING LICENSE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EF-ISE-SYSTEM-NL | 功能描述:SOFTWARE ISE SYS EDITION RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| EFJ02-001M | 制造商:Black Box Corporation 功能描述:TOSLINK TO MINI PLUG PATCH COR |
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