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参数资料
型号： EFM32-TG210F32-SK
厂商： Energy Micro
文件页数： 125/136页
文件大小： 0K
描述： IC MICRO KIT GECKO 32QFN
标准包装： 1
系列： Tiny Gecko
套件类型： 微控制器
值： 2 件 - 闪存 - 32KB
包装： 纸板盒
安装类型： 表面贴装
包括封装： 32-QFN
工具箱内容： (2) 914-1034-2-ND - MCU 32BIT 32KB FLASH 32-QFN
其它名称： 914-1019
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
89
www.energymicro.com
Address
Name
Type
Required
privilege
Reset value
Description
0XE000E200
-
0XE000E204
ISPR0-
ISPR1
RW
Privileged
0x00000000
Section 4.2.4 (p. 90)
0XE000E280
-
0XE000E284
ICPR0-
ICPR1
RW
Privileged
0x00000000
Section 4.2.5 (p. 91)
0xE000E300
-
0xE000E304
IABR0-
IABR1
RO
Privileged
0x00000000
Section 4.2.6 (p. 91)
0xE000E400
-
0xE000E400+4xm
IPR0-
IPRm
RW
Privileged
0x00000000
Section 4.2.7 (p. 92)
1
0xE000EF00
STIR
WO
Configurable
2
0x00000000
Section 4.2.8 (p. 93)
1m=(n-1)/4, where n denotes the number of interrupts given in Table 1.1 (p. 5) .
2See the register description for more information.
4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of
32-bit integers, so that:
ISER[0] to ISER[1]corresponds to the registers ISER0-ISER1
ICER[0] to ICER[1]corresponds to the registers ICER0-ICER1
ISPR[0] to ISPR[1]corresponds to the registers ISPR0-ISPR1
ICPR[0] to ICPR[1]corresponds to the registers ICPR0-ICPR1
IABR[0] to IABR[1]corresponds to the registers IABR0-IABR1
the 8-bit fields of the Interrupt Priority Registers map to an array of 8-bit integers, so that the array
IP[0]
to IP[n-1] corresponds to the registers IPR0-IPRm (m=(n-1)/4, where n denotes the number
of interrupts given by Table 1.1 (p. 5) ), and the array entry IP[N] holds the interrupt priority for
interrupt N.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For
more information see the description of the NVIC_SetPriority function in Section 4.2.10.1 (p. 94)
. Table 4.3 (p. 89) shows how the interrupts, or IRQ numbers, map onto the interrupt registers and
corresponding CMSIS variables that have one bit per interrupt.
Table 4.3. Mapping of interrupts to the interrupt variables
CMSIS array elements
1
Interrupts
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
0-31
ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
32-63
ISER[1]
ICER[1]
ISPR[1]
ICPR[1]
IABR[1]
1Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
4.2.2 Interrupt Set-enable Registers
The ISER0 and ISER1 registers enable interrupts, and show which interrupts are enabled. See:
the register summary in Table 4.2 (p. 88) for the register attributes
Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
SETENA bit s
31
0
相关PDF资料
PDF描述
1267 X 6" TAPE ALUMINUM FOIL 6" X 1FT
7810 0.25MM ECAP COND PAD .25MM 7.7" X 10"
7810 0.20MM ECAP COND PAD .20MM 7.7" X 10"
1170 X 6" TAPE FOIL .002" 6" X 18YDS
EFM32-TG110F32-SK IC MICRO KIT GECKO 24QFN
相关代理商/技术参数
参数描述
EFM32TG210F32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN
EFM32TG210F8 功能描述:ARM微控制器 - MCU 8KB Flash 2KB RAM RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT
EFM32TG210F8-QFN32 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 32QFN
EFM32TG210F8-QFN32T 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays
EFM32TG210F8-QFN32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 8KB FLASH 32QFN
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