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参数资料
型号： EFM32TG222F32
厂商： Energy Micro
文件页数： 124/136页
文件大小： 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
特色产品： EFM32 Tiny Gecko
标准包装： 1
系列： Tiny Gecko
核心处理器： ARM? Cortex?-M3
芯体尺寸： 32-位
速度： 32MHz
连通性： I²C，IrDA，智能卡，SPI，UART/USART
外围设备： 欠压检测/复位，DMA，I²S，POR，PWM，WDT
输入/输出数： 37
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
数据转换器： A/D 4x12b，D/A 1x12b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 48-TQFP
包装： 标准包装
其它名称： 914-1029-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
88
www.energymicro.com
4 The Cortex-M3 Peripherals
4.1 About the peripherals
The address map of the Private peripheral bus (PPB) is:
Table 4.1. Core peripheral register regions
Address
Core peripheral
Description
0xE000E008
-0xE000E00F
System control block
Table 4.12 (p. 94)
0xE000E010
-0xE000E01F
System timer
Table 4.32 (p. 111)
0xE000E100
-0xE000E4EF
Nested Vectored Interrupt Controller
Table 4.2 (p. 88)
0xE000ED00
-0xE000ED3F
System control block
Table 4.12 (p. 94)
0xE000ED90
-0xE000EDB8
Memory protection unit
Section 4.5.1 (p. 114)
1
0xE000EF00
-0xE000EF03
Nested Vectored Interrupt Controller
Table 4.2 (p. 88)
1Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory protection unit (MPU). Register
will read as zero if MPU is not present.
In register descriptions:
the register type is described as follows:
RW Read and write.
RO Read-only.
WO Write-only.
the required privilege gives the privilege level required to access the register, as follows:
Privileged
Only privileged software can access the register.
Unprivileged
Both unprivileged and privileged software can access the register.
4.2 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The
NVIC supports:
The number of interrupts given by Table 1.1 (p. 5) .
A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling. The hardware
implementation of the NVIC registers is:
Table 4.2. NVIC register summary
Address
Name
Type
Required
privilege
Reset value
Description
0xE000E100
-
0xE000E104
ISER0-
ISER1
RW
Privileged
0x00000000
Section 4.2.2 (p. 89)
0XE000E180
-
0XE000E184
ICER0-
ICER1
RW
Privileged
0x00000000
Section 4.2.3 (p. 90)
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EFM32TG222F32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 48TQFP
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