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| 型号： | EK42552-01 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR 42552 RF SWITCH |
| 标准包装： | 1 |
| 系列： | UltraCMOS™, HaRP™ |
| 类型： | 开关，SPDT |
| 频率： | 0Hz ~ 7.5GHz |
| 适用于相关产品： | PE42552 |
| 已供物品： | 板 |
| 其它名称： | EK42552-1 EK42552-1-ND PE42552 EK |
PE42552
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
V DD
Parameter/Conditions
Power supply voltage
Min
-0.3
Max
4.0
Units
V
GND
RF1
GND
GND
1
2
3
4
12
11
10
9
GND
RF2
GND
GND
V I
V CTRL
V LS
T ST
P IN
Voltage on any input except for
CTRL and LS inputs
Voltage on CTRL input
Voltage on LS input
Storage temperature range
Input Power:
9 kHz ≤ 1 MHz
1 MHz ≤ 7.5 GHz
-0.3
-65
V DD +
0.3
4.0
4.0
150
fig. 4,5
30
V
V
V
°C
dBm
dBm
V ESD
ESD voltage (HBM) 1
ESD voltage (Machine Model)
1000
100
V
V
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Table 2. Pin Descriptions
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
Pin No.
2
1, 3, 4, 5, 6,
8, 9, 10, 12
7
11
13
14
15
16
Pin Name
RF1
GND
RFC
RF2
V SS
CTRL
LS
V DD
Description
RF Port 1
Ground
RF Common
RF Port 2
Negative supply voltage or GND
connection (Note 1)
CMOS level:
Logic Select - Used to determine
the definition for the CTRL pin (see
Table 5)
Nominal 3.3 V supply connection
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Note: 1. Use VSS (pin 13, VSS = -VDD) to bypass and disable
internal negative voltage generator. Connect VSS (pin 13) to GND
(VSS = 0V) to enable internal negative voltage generator.
Table 3. Operating Ranges
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Parameter
V DD Positive Power Supply Voltage
V SS Negative Power Supply Voltage
(external power supply used)
Min
3.0
-3.6
Typ
3.3
-3.3
Max
3.6
-3.0
Units
V
V
LS
0
0
1
1
CTRL
0
1
0
1
RFC-RF1
off
on
on
off
RFC-RF2
on
off
off
on
RF Power In (P IN ):
V SS Negative Power Supply Voltage
(internal power supply used)
I DD Power Supply Current
(V SS = 0V, Temp = +85 °C)
I SS Negative Supply
(V SS = -V DD , Temp = 25 °C)
Control Voltage High
Control Voltage Low
T OP Operating temperature range
1
9 kHz ≤ 1 MHz
1 MHz ≤ 7.5 GHz
-0.1
0.7xV DD
-40
0.0
15
-10
25
0.0
120
-40
0.3xV DD
85
fig. 4,5
30
V
μ A
μ A
V
V
°C
dBm
dBm
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
Spurious Performance
The typical spurious performance of the PE42552 is
-116 dBm when VSS=0V (pin 13 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
Switching Frequency
Note: 1. Please consult low frequency graphs on page 3 for
recommended operating power level.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE42552 in
the 16-lead 3x3mm QFN package is MSL1.
?2008 Peregrine Semiconductor Corp. All rights reserved.
The PE42552 has a maximum 25 kHz switching rate
when the internal negative voltage generator is used
(pin 13=GND). The rate at which the PE42552 can be
switched is only limited to the switching time (Table 1) if
an external negative supply is provided at
(pin13=VSS).
Document No. 70-0246-03 │ UltraCMOS? RFIC Solutions
Page 2 of 9
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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