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参数资料
| 型号： | EK64905-11 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR 64904 W/CABLES |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 类型： | 数字调谐式电容器 |
| 频率： | 100MHz ~ 3GHz |
| 适用于相关产品： | PE64905 |
| 已供物品： | 板 |
| 其它名称： | 101-0597-02 |
PE64905
Product Specification
Layout Recommendations
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF- pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
Figure 19. Recommended Schematic of
Multiple DTCs
Evaluation Board
The 101-0597 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Series (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B ( ε r = 3.48) and 2 inner
layers of FR4 ( ε r = 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using a
trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
Figure 21. Evaluation Board
Figure 20. Recommended Layout of
Multiple DTCs
101-0597
Document No. 70-0335-06 │ www.psemi.com
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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