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参数资料
| 型号： | EL1056AC |
| 英文描述： | Monolithic High-Speed Pin Driver |
| 中文描述： | 单片高速管脚驱动 |
| 文件页数： | 16/16页 |
| 文件大小： | 311K |
| 代理商： | EL1056AC |
EL1056ACEL1056C
Monolithic High-Speed Pin Driver
Applications Information
Functional Description
The EL1056 is a fully integrated pin driver for
automatic test systems Pin drivers are essential-
ly pulse generators whose high and low levels can
be externally programmed and accurately switch-
ed in time as well as incorporating an output
switch to disconnect the driver from a measure-
ment bus
Additionally
the EL1056 has pro-
grammable slewrate
Control Voltage Inputs
The analog level inputs are named VINH and
VINL and the output replicates them as con-
trolled by logic inputs The analog inputs are
buffered and have bandwidths of 35 MHz and
slewrates of 25V
ms For full slewrate 4V of
headroom should be given to the inputs that is
VINH should be 4V less than Va or Ba and
VINL should be 4V more positive than Vb or
Bb At lower slewrates (ISR e 500 mA or less)
3V of headroom will suffice Insufficient head-
room causes distorted output waveforms or delay
errors in output transitions VINH may be lower
in voltage than VINL but the output will not fol-
low the control logic correctly
Furthermore
VINH should be 200 mV more positive than VINL
(the minimum output amplitude) for accurate
switching
Logic Inputs
The logic inputs are all differential types with
both NPN and PNP transistors connected to
each terminal They are optimized for differential
ECL drive which optimizes a to b edge delay
time matching Larger logic levels can introduce
feedthrough glitches into the output waveform
For CMOS input logic levels an ECL output
waveform
will
show
feedthrough
when
the
input risetime is shorter than 8 ns differential or
single-ended CMOS output swings show less ab-
erration and the EL1056 can toleratea4ns
single-ended risetime or 2 ns risetime for differ-
ential inputs Attenuating CMOS or TTL inputs
to 1 Vp-p will eliminate all logic feedthrough as
shown in Figure 1
1056 – 2
1056 – 3
Alternate Logic Interface
Figure 1
Slewrate Control
The slewrate is controlled by the ISR input This
is a current input and scales the output slewrate
by a nominal 125VnsmA The slewrate main-
tains calibration and symmetry to at least as slow
as 02Vns The practical upper end of ISR is
1 mA and supply current increases with increas-
ing ISR
The ISR control can be used to adjust individual
pin drivers to a system standard by adjusting
the value of its series resistor Slewrate can also
be slowed to reduce output ringing and crosstalk
With ECL output swings there is not enough
voltage excursion to incur slewrate delays to 50%
logic threshold The risetime delays and disper-
sions do not degrade with reasonably reduced
ISR and overshoot will reduce markedly An ISR
of 350
mA produces a very good ECL output and
driver dissipation is also reduced
9
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相关代理商/技术参数 |
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| EL1056ACM | 制造商:ELANTEC 制造商全称:ELANTEC 功能描述:Monolithic High-Speed Pin Driver |
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