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参数资料
| 型号： | EL4102CU |
| 英文描述： | 500MHz Video Front End: 4-1 MUX, VGA & DC-Restore |
| 中文描述： | 500MHz的前端视频：4-1多路复用器，VGA端口 |
| 文件页数： | 8/9页 |
| 文件大小： | 272K |
| 代理商： | EL4102CU |
8
EL4102C - Preliminary
500MHz Video Front End: 4-1 MUX, VGA & DC-Restore
EL
4102C
-
Pre
liminary
Applications Information
Using the Serial Data Output Connection for a
Multi-chip Design
In a system design that uses three chips, (i.e. RGB,
YUV, YPrPb systems) the control signal may be "daisy
chained" through the three chips. This gives an advan-
tage in that the control will be updated simultaneously
on the three channels.
The serial data out (SDO) of chip one is connected to the
serial data in (SDI) of chip two, similarly, chip two SDO
is connected to SDI on chip three. The clock (SCLK)
and enable (/ENB) signals are connected in parallel to all
three chips. See figure yy for suggested interconnect of
the control signals.
Figure xx shows the control signal waveforms when
using this configuration. Note, that the last data bit
clocked into the three chips occurs on the last positive
clock edge that is within the enabled period. This will be
D0 in the first chip, D8 and D16 on the second two
chips. The rising edge of /ENB will then simultaneously
transfer the data internally to the chip. Typically the data
for each chip is held as an image in the micro-controller
system; the load operation would prepare the update
information as a 24-bit word ready for shifting into the
three chips.
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