参数资料
| 型号： | EL4585CSZ-T13 |
| 厂商： | Intersil |
| 文件页数： | 2/15页 |
| 文件大小： | 0K |
| 描述： | IC GENLOCK HORZ 8FSC 16-SOIC |
| 标准包装： | 2,500 |
| 类型： | 锁相环路（PLL） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | CMOS，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 36MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
10
FN7175.4
September 3, 2009
C1 is to adjust the center frequency, C2 DC isolates the
control from the oscillator, and V1 is the primary control
device. C2 should be much larger than CV so that V1 has
maximum modulation capability. The frequency of oscillation
is given by Equation 4:
Choosing Loop Filter Components
The PLL, VCO, and loop filter can be described as:
Where:
Kd = phase detector gain in A/rad
F(s) = loop filter impedance in V/A
KVCO = VCO gain in rad/s/V
N = Total internal or external divisor (see 3 below)
It can be shown that for the loop filter shown in Equation 5:
Where
ω
n = loop filter bandwidth, and ζ = loop filter damping
factor.
1. Kd = 300A/2πrad = 4.77e-5A/rad for the EL4585.
2. The loop bandwidth should be about HSYNC
frequency/20, and the damping ratio should be 1 for
optimum performance. For our example,
ωn = 15.734kHz/20=787 Hz≈5000 rad/S.
3. N = 910x2 = 1820 from Table 1.
4. KVCO represents how much the VCO frequency changes
for each volt applied at the control pin. It is assumed (but
probably is not) linear about the lock point (2.5V). Its
value depends on the VCO configuration and the varactor
transfer function CV =F(VC), where VC is the reverse
bias control voltage, and CV is varactor capacitance.
Since F(VC) is nonlinear, it is probably best to build the
VCO and measure KVCO about 2.5V. The results of one
such measurement are shown below. The slope of the
curve is determined by linear regression techniques and
equals KVCO. For our example, KVCO = 9.06 Mrad/s/V.
We choose R3 = 43kΩ for convenience.
6. Notice R2 has little effect on the loop filter design. R2
should be large, around 100k, and can be adjusted to
compensate for any static phase error T
θ at lock, but if
made too large, will slow loop response. If R2 is made
smaller, T
θ (see “Timing Diagrams” on page 5) increases,
and if R2 increases, Tθ decreases. For LDET to be low at
lock, |T
θ| < 50ns. C4 is used mainly to attenuate high
frequency noise from the charge pump. The effect these
components have on-time to lock is illustrated in
Figure 12.
Lock Time
Let T = R3C3. As T increases, damping increases, but so
does lock time. Decreasing T decreases damping and
speeds up loop response, but increases overshoot and thus
increases the number of hunting oscillations before lock.
Critical damping (
ζ=1) occurs at minimum lock time.
Because decreased damping also decreases loop stability, it
is sometimes desirable to design slightly overdamped (
ζ>1),
trading lock time for increased stability.
FIGURE 10.
COLPITTS OSCILLATOR
F
1
2
π LC
T
-----------------------
=
C
T
C
1C2Cv
C
1 C2
()
C
1CV
()
C
1CV
()
++
--------------------------------------------------------------------------
=
(EQ. 4)
C
3
K
dKVCO
N
ω
n
2
------------------------ C
4
,
C
3
10
------- R
3
,
2N
ζω
n
K
dKVCO
------------------------
==
=
(EQ. 5)
N
F
VCO
F
Hsync
--------------------
28.636M
15.73426k
----------------------------
1820
910x2
==
=
(EQ. 6)
FIGURE 11.
FOSC vs VC, LC VCO
C
3
K
dKVCO
N
ω
n
2
------------------------
4.77e
5
–
() 9.06e6
()
1820
() 5000
()
2
------------------------------------------------------
0.01
μF
==
=
C
4
C
3
10
-------
0.001
μF
==
R
3
2N
ζω
2
K
dKVCO
------------------------
2
() 1820
() 1
() 5000
()
4.77e
5
–
() 9.06e6
()
------------------------------------------------------
42.1k
Ω
==
=
(EQ. 7)
EL4585
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