参数资料
型号: EL5225IRZ-T13
厂商: Intersil
文件页数: 8/12页
文件大小: 0K
描述: IC VREF GEN 10CH TFT-LCD 24TSSOP
标准包装: 2,500
应用: 转换器,TFT,LCD
输入电压: 5 V ~ 16.5 V
输出数: 10
输出电压: 0.5 V ~ 14.95 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
EL5225
Block Diagram
REFERENCE HIGH
OUTA
OUTB
OUTH
EIGHT
CHANNEL
MEMORY
VOLTAGE
SOURCES
OUTI
OUTJ
REFERENCE LOW
REFERENCE DECOUPLE
CLK
SDI
LOAD
CONTROL IF
SDO
FILTER
CHANNEL OUTPUTS
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Electrical Characteristics for
details).
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5 ? and
EXT_OSC
and 4.2ms depending on the absolute timing relative to the
update cycle.
Output Stage and the Use of External Oscillator
Simplified output sample and hold amp stage for one
channel.
CH
50 ? ).
Each of the channels is updated on a continuous cycle, the
1.3V
+
-
S 1
1.3V
+
-
V OUT
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
V IN
+
-
S 2
OSC
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48μs. In the worst-case
scenario, this will be 480μs when the data has just missed
the cycle.
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 3.8ms
8
FIGURE 11.
The output voltage is generated from the DAC, which is V IN
at the above circuit. The refreshed switches are controlled
by the internal or external oscillator signal. When the OSC
clock signal is low, the switch S 1 and S 2 are closed. The
output V OUT = V IN and at the same time the sample and
hold cap CH is being charged. When the OSC clock signal is
high, the refreshed switch S 1 and S 2 are opened and the
output voltage is maintained by CH. This refreshed process
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