参数资料
型号: EL5225IRZ
厂商: Intersil
文件页数: 6/12页
文件大小: 0K
描述: IC VOLT GEN 10CH TFT-LCD 24TSSOP
标准包装: 62
应用: 转换器,TFT,LCD
输入电压: 5 V ~ 16.5 V
输出数: 10
输出电压: 0.5 V ~ 14.95 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
EL5225
The SCLK is disabled internally when the ENA is high. The
TABLE 1. CONTROL BITS LOGIC TABLE
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5225
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5225 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table)
? Bit 15 is always set to a zero
? Bit 14 controls the source of the clock, see the next
section for details
? Bits 13 through 10 select the channel to be written to,
BIT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
NAME
Test
Oscillator
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Always 0
0 = Internal, 1 = External
Channel Address
Channel Address
Channel Address
Channel Address
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
these are binary coded with channel A = 0, and channel
H=7
? The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in the table of Serial Programming
Examples
Serial Timing Diagram
ENA
t HE
t SE
T
t r
t f
t HE
t SE
SCLK
t SD
t HD
t w
SDI
B15
B14
B13
B12-B2
B1
B0
t
MSB
6
Load MSB first, LSB last
LSB
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