参数资料
型号: EL5412IRE-T7
厂商: Intersil
文件页数: 8/8页
文件大小: 0K
描述: IC OP AMP 40MHZ R-R 14-HTSSOP
标准包装: 1,000
放大器类型: 电压反馈
电路数: 4
输出类型: 满摆幅
转换速率: 55 V/µs
增益带宽积: 22MHz
-3db带宽: 40MHz
电流 - 输入偏压: 2nA
电压 - 输入偏移: 3000µV
电流 - 电源: 2.5mA
电流 - 输出 / 通道: 65mA
电压 - 电源,单路/双路(±): 4.5 V ~ 16.5 V,±2.25 V ~ 8.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP (0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 14-HTSSOP
包装: 带卷 (TR)
8
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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FN7394.1
December 22, 2004
Where:
i = Channel 1 to 4
VS = Total supply voltage
ISMAX = Maximum supply current per amplifier
VOUTi = Maximum output voltage of the application
ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figure 10
and Figure 11 provide a convenient way to see if the device
will overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 10 and 11.
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers be configured
as a unity gain follower. The inverting input should be directly
connected to the output and the non-inverting input tied to
the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5412 can provide gain at high frequency. As with any
high-frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1F ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7F tantalum capacitor should then be
connected in parallel, placed in the region of the amplifier.
One 4.7F capacitor may be used for multiple devices. This
same capacitor combination should be placed at each
supply pin to ground if split supplies are to be used.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - HTSSOP
EXPOSED DIEPAD SOLDERED TO PCB PER
JESD51-5
3.5
3
2.5
1.5
1
0.5
0
255075
100
150
AMBIENT TEMPERATURE (°C)
POWER
DIS
S
IP
AT
ION
(W)
125
85
2
2.632W
θ
JA =
38°
C/W
HT
SS
OP
14
100
MAX
TJ=125°C
θJA=1
00°C/W
1.0W
TSSOP
14
400
800
P
O
WER
DIS
S
IP
A
T
ION
(m
W)
0
1200
1000
600
200
PACKAGE MOUNTED ON A JEDEC JESD51-3
LOW EFFECTIVE THERMAL CONDUCTIVITY
TEST BOARD
606mW
θ
JA=16
5°C
/W
TSS
OP1
4
MAX
TJ=125°C
50
150
AMBIENT TEMPERATURE (°C)
100
025
75
125
85
694mW
θ
JA =1
44°C
/W
HT
SS
OP
14
EL5412
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