参数资料
| 型号： | EL5825ILZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | IC VREF GEN 8CH TFT-LCD 24-QFN |
| 标准包装： | 1,000 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 16.5 V |
| 输出数： | 8 |
| 输出电压： | 0.5 V ~ 14.95 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 带卷 (TR) |
EL5825
Absolute Maximum Ratings (T A = 25°C)
Supply Voltage between V S and GND. . . . . . . . . . . . . . . . . . . .+18V
Supply Voltage between V SD and GND . . . . . . . V S and +7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T J = T C = T A
Electrical Specifications
V S = 15V, V SD = 5V, V REFH = 13V, V REFL = 2V, R L = 1.5k ? and C L = 200pF to 0V, T A = 25°C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I S
I SD
Supply Current
Digital Supply Current
No load
7.6
0.17
9
0.35
mA
mA
ANALOG
V OL
Output Swing Low
Sinking 5mA (V REFH = 15V, V REFL = 0)
50
150
mV
V OH
I SC
PSRR
t D
V AC
V DROOP
R INH
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy
Droop Voltage
Input Resistance @ V REFH , V REFL
Sourcing 5mA (V REFH = 15V, V REFL = 0)
R L = 10 ?
V S + is moved from 14V to 16V
14.85
100
45
14.95
140
60
4
20
1
34
2
V
mA
dB
ms
mV
mV/ms
k ?
REG
BG
Load Regulation
Band Gap
I OUT = 5mA step
1.1
0.5
1.3
1.5
1.6
mV/mA
V
DIGITAL
V IH
V IL
F CLK
t S
t H
t LC
t CE
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
V SD -
20%
20
20
20
20
20%*
V SD
5
V
V
MHz
ns
ns
ns
ns
t DCO
R SDIN
Clock to Out Delay Time
S DIN Input Resistance
Negative edge of SCLK
10
1
ns
G ?
2
FN7005.4
June 24, 2005
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