参数资料
| 型号： | EL7520ILZ-T13 |
| 厂商： | Intersil |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC/DC 4-CHAN 20-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，TFT LCD |
| 输入电压： | 3 V ~ 5.5 V |
| 输出数： | 4 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
EL7520, EL7520A
V ON = V REF × ? 1 + ---------- ?
V OFF = V REFN + ---------- × ( V REFN – V REF )
V LOGIC = V REF × ? ?
? R 42 ?
N POSITIVE ≥ --------------------------------------------------------------
N NEGATIVE ≥ -------------------------------------------------
C OUT ≥ ------------------------------------------------------
under the low dropout condition (forced beta of 10). Typical
V LOGIC voltage supported by EL7520, EL7520A range from
+1.3V to V DD -0.2V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 25% below the 1.2V reference.
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of
V ON , V OFF , and V LOGIC are determined by the following
equations:
? R 12 ?
? R 11 ?
R 22
R 21
1 + ----------
? R 41 ?
Where V REF = 1.2V, V REFN = 0.2V.
Charge Pump
To generate an output voltage higher than V BOOST , single or
multi stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
V OUT + V CE – V INPUT
V INPUT – 2 × V F
where V CE is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
the transistor. V F is the forward-voltage of the charge pump
rectifier diode.
The number of negative charge pump stages is given by:
V OUTPUT + V CE
V INPUT – 2 × V F
To achieve high efficiency and low material cost, the lowest
number of charge pump stages, which can meet the above
requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
I OUT
2 × V RIPPLE × f OSC
Where f SOC is the switching frequency.
14
Start-Up Sequence
Figures 30 and 31 show detailed start-up sequence
waveforms, EL7520 and EL7520A, respectively. For a
successful power-up, there should be six peaks at V CDLY .
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (V DD ) exceeds 2.5V, an internal current source
starts to charge C DLY to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
C DLY ramp will be delayed until EN goes high.
The first four ramps on C DLY (two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on C DLY or V REF . If a fault is
detected, the outputs and the input protection will turn off and
the chip will power down. For EL7520A, V REF will stay on.
If no fault is found, C CDLY continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
V REF and over temperature. At the peak of the second ramp,
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V BOOST before V BOOST is enabled internally. Its rate of turn
on is controlled by C o . When a fault is detected, Q1 will turn
off and disconnect the inductor from V IN .
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V IN . Initially the boost is not
enabled so V BOOST rises to V IN -V DIODE through the output
diode. Hence, there is a step at V BOOST during this part of the
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A VDD .
For EL7520, V BOOST and V LOGIC soft-start at the beginning
of the third ramp. The soft-start ramp depends on the value
of the C DLY capacitor. For C DLY of 220nF, the soft-start time
is ~2ms. EL7520A is the same as EL7520 except that V REF
and V LOGIC turn on once input voltage exceeds 2.5V.
V OFF turns on at the start of the fourth peak. At the fifth
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed V BOOST output.
V ON is enabled at the beginning of the sixth ramp. A VDD ,
PG, V OFF , DELB and V ON are checked at end of this ramp.
FN7318.0
July 12, 2005
相关PDF资料 |
PDF描述 |
|---|---|
| NCP4640H030T1G | IC REG LDO 3V 50MA SOT89-5 |
| EL7520AILZ-T7 | IC CTRLR DC/DC 4-CHAN 20-QFN |
| EL7520AILZ-T13 | IC CTRLR DC/DC 4-CHAN 20-QFN |
| GMC31DRXS-S734 | CONN EDGECARD 62POS DIP .100 SLD |
| ISL6556BCRZA-T | IC CTRLR MULTIPHASE VRM10 32-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EL7520ILZ-T7 | 功能描述:电流型 PWM 控制器 EL7520ILZ 4-CH DC-DC CNTRLR RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| EL7530 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Monolithic 600mA Step-Down Regulator with Low Quiescent Current |
| EL7530_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Monolithic 600mA Step-Down Regulator with Low Quiescent Current |
| EL7530EVAL1 | 功能描述:EVALUATION BOARD FOR EL7530 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| EL7530IL | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Monolithic 600mA Step-Down Regulator with Low Quiescent Current |
发布紧急采购，3分钟左右您将得到回复。