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| 型号： | EL7531IYZ |
| 厂商： | Intersil |
| 文件页数： | 10/11页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 10MSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 10-MSOP |
| 产品目录页面： | 1242 (CN2011-ZH PDF) |
EL7531
f Z = ----------------------
f P = ---------------------------------------
V O = 0.8 × ? 1 + ------- ?
I INRMS = ----------------------------------------------- × I O
( V IN – V O ) × V O
L × V IN × f S
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Thermal Performance
The EL7531 is available in a fused-lead MSOP10 package.
Compared with regular MSOP10 package, the fused- lead
package provides lower thermal resistance. The θ JA is
100°C/W on a 4-layer board and 125°C/W on 2-layer board.
Maximizing the copper area around the pins will further
improve the thermal performance.
Power Good Output
The PG (pin 8) output is used to indicate when the output
voltage is properly regulating at the desired set point. It is an
open-drain output that should be tied to VIN or VCC through
a 100k Ω resistor. If no faults are detected, EN is high, and
the output voltage is within ~5% of regulation, the PG pin will
be allowed to go high. Otherwise, the open-drain NMOS will
pull PG low.
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
? R 2 ?
? R 1 ?
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
We recommend 10μf to 22μF multi-layer ceramic capacitors
with X5R or X7R rating for both the input and output
capacitors, and 1.5 to 2.2μH for the inductor.
The RMS current present at the input capacitor is decided by
the following formula:
V O × ( V IN – V O )
V IN
This is about half of the output current I O for all the V O . This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
Δ I IL = --------------------------------------------
L is the inductance
f S the switching frequency (nominally 1.4MHz)
10
The inductor must be able to handle I O for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C 4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C 4 should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
1
2 π R 2 C 4
Over a normal range of R 2 (~10-100k), C 4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R 1
and R 2 , which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
1
2 π ( R 1 R 2 ) C 4
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to V IN and PGND pins
as possible
3. Make the following PC traces as small as possible:
4. from LX pin to L
5. from C O to PGND
6. If used, connect the trace from the FB pin to R 1 and R 2
as close as possible
7. Maximize the copper area around the PGND pin
8. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7531 Application Brief.
FN7428.9
July 13, 2006
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