参数资料
型号: EL7583IR
厂商: Intersil
文件页数: 13/16页
文件大小: 0K
描述: IC CONV DC/DC 3-CHAN 20-TSSOP
标准包装: 74
应用: 转换器,TFT,LCD
输入电压: 2.7 V ~ 14 V
输出数: 2
输出电压: 5 V ~ 17 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 管件
EL7583
Two-Stage Negative Charge Pump Circuit
V DDN
R ONP
DRVN
5V-17V
V LX
C CPN
V OFF
R ONN
V SSN
FBN
+
C CPN
C OUT2
C OUT2
R 21
V OFF ( max ) ≥ I OUT × 2 × ( R ONN + R ONP ) + 2 × V DIODE - I OUT × -------------------------------------------- - I OUT × ------------------------------------------------ -
0.5 × F × C 0.5 × F × C
V DDN - N × V LX ( max ) + N × ? 2 × V DIODE + I OUT × -------------------------------------------- + I OUT × ------------------------------------------------ ?
? 0.5 × F × C 0.5 × F × C ?
V OFF = -V REF × ----------
-
R 22
V REF
The maximum V OFF output voltage for N+1 stage charge pump is:
1 1
S CPN S OUT2
1 1
S CPN S OUT2
R 21 and R 22 determine V OFF output voltage:
R 21
R 22
where V REF is 1.310V.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
130°C and 90°C respectively.
PCB Layout Guidelines
Careful layout is critical in the successful operation of the
application. The following layout guidelines are
recommended to achieve optimum performance.
? V REF and V DDB bypass capacitors should be placed next
to the pins.
? Place the boost converter diode and inductor close to the
LX pins.
? Place the boost converter output capacitor close to the
PGND pins.
? Locate feedback dividers close to their respected
feedback pins to avoid switching noise coupling into the
high impedance node.
? Switching output PCB traces should not cross, or be laid
out adjacent to, feedback traces without using a grounded
13
shielding trace or layer. This is to prevent undesirable
switching interactions coupling into the feedback inputs.
? Place the charge pump feedback resistor network after the
diode and output capacitor node to avoid switching noise.
? All low-side feedback resistors should be connected
directly to V SSB . V SSB should be connected to the power
ground close at one point only.
A demo board is available to illustrate the proper layout
implementation.
FN7335.5
May 12, 2006
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