参数资料
| 型号： | EL7585ILZ-T7 |
| 厂商： | Intersil |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY TFT-LCD 20-QFN |
| 标准包装： | 1,000 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 3 V ~ 5 V |
| 输出数： | 4 |
| 输出电压： | 5.5 V ~ 20 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
EL7585
C OUT ≥ ------------------------------------------------------
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
The EL7585 V ON and V OFF architecture uses LX switching
edges to drive diode charge pumps from which LDO
regulators generate the V ON and V OFF supplies. It can be
appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
operation at light A VDD boost load currents, then this may
affect the performance of V ON and V OFF regulation -
depending on their exact loading conditions at the time.
To optimize V ON /V OFF regulation, the boundary of
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V IN ,
V OUT , switching frequency and the A VDD current loading, to
be in continuous operation.
The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:
I(A VDD _load) > D*(1-D)*V IN /(2*L*F OSC )
where the duty cycle, D = (A VDD - V IN )/A VDD
For example, with V IN = 5V, F OSC = 1.0MHz and A VDD =
12V we find continuous operation of the boost converter can
be guaranteed for:
L = 10μH and I(A VDD ) > 61mA
L = 6.8μH and I(A VDD ) > 89mA
L = 3.3μH and I(A VDD ) > 184mA
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
I OUT
2 × V RIPPLE × f OSC
where f OSC is the switching frequency.
Start-Up Sequence
Figure 26 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V CDLY .
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
If EN is L, the device is powered down. If EN is H, and the
input voltage (V DD ) exceeds 2.5V, an internal current source
starts to charge C DLY to an upper threshold using a fast
ramp followed by a slow ramp. If EN is low at this point, the
C DLY ramp will be delayed until EN goes high.
The first four ramps on C DLY (two up, two down) are used to
initialize the fault protection switch and to check whether
there is a fault condition on C DLY or V REF . If a fault is
14
detected, the outputs and the input protection will turn off
and the chip will power down.
If no fault is found, C CDLY continues ramping up and down
until the sequence is completed.
During the second ramp, the device checks the status of
V REF and over temperature. At the peak of the second ramp,
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V BOOST before V BOOST is enabled internally. Its rate of turn
on is controlled by C o . When a fault is detected, M1 will turn
off and disconnect the inductor from V IN .
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V IN . Initially the boost is not
enabled so V BOOST rises to V IN -V DIODE through the output
diode. Hence, there is a step at V BOOST during this part of the
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A VDD .
For EL7585, V BOOST and V LOGIC soft-start at the beginning
of the third ramp. The soft-start ramp depends on the value
of the C DLY capacitor. For C DLY of 220nF, the soft-start time
is ~2ms.
V OFF turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q4 to generate a delayed V BOOST output.
V ON is enabled at the beginning of the sixth ramp. A VDD ,
PG, V OFF , DELB and V ON are checked at end of this ramp.
Fault Protection
During the startup sequence, prior to BOOST soft-start,
V REF is checked to be within ±20% of its final value and the
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
If C DELAY is shorted low, then the sequence will not start,
while if C DELAY is shorted H, the first down ramp will not
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C DLY , DELB, FBP, FBL, FBN, V REF ,
FBB and PG and checks for faults. During this time, the
voltage on the C DLY capacitor remains at 1.15V until either a
fault is detected, or the EN pin is pulled low.
A fault on C DELAY , V REF or temperature will shut down the
chip immediately. If a fault on any other output is detected,
C DELAY will ramp up linearly with a 5μA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C DLY capacitor returns to 1.15V.
FN7345.2
March 9, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EL7586 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:TFT-LCD Power Supply |
| EL7586_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:TFT-LCD Power Supply |
| EL7586A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:TFT-LCD Power Supply |
| EL7586AILZ | 功能描述:直流/直流开关调节器 EL7586AILZ TFT-LCD PWR SUPY RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| EL7586AILZ-T13 | 功能描述:直流/直流开关调节器 EL7586AILZ TFT-LCD P PWR SUPY RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
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