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参数资料
型号： EM6603TP24B
英文描述： Microcontroller
中文描述： 微控制器
文件页数： 23/39页
文件大小： 675K
代理商： EM6603TP24B
EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
1
OPERATING MODES
5
1.1
STANDBY MODE
5
1.2
SLEEP MODE
5
2
POWER SUPPLY
5
3
RESET
6
3.1
OSCILLATION DETECTION CIRCUIT
6
3.2
RESET PIN
6
3.3
INPUT PORT (PA0..PA3) RESET
7
3.4
WATCHDOG TIMER RESET
7
3.5
CPU STATE AFTER RESET
7
4
OSCILLATOR
8
4.1
PRESCALER
8
5
WATCHDOG TIMER
8
6
INPUT AND OUTPUT PORTS
9
6.1
PORTA9
6.2
PORTA REGISTERS
10
6.3
PORTB11
6.4
PORTB REGISTERS
11
6.5
PORTC12
6.6
PORTC REGISTERS
12
6.7
PORTD14
6.8
PORTD REGISTERS
14
7
BUZZER
15
7.1
BUZZER REGISTER
15
8
TIMER/EVENT COUNTER
16
8.1
TIMER/COUNTER REGISTERS
17
9
INTERRUPT CONTROLLER
18
9.1
INTERRUPT CONTROL REGISTERS
18
10
SUPPLY VOLTAGE LEVEL DETECTOR (SVLD)
20
10.1
SVLD REGISTER
20
11
SERIAL (OUTPUT) WRITE BUFFER – SWB
21
11.1
SWB AUTOMATIC SEND MODE
23
11.2
SWB INTERACTIVE SEND MODE
25
12
STROBE / RESET OUTPUT
26
13
TEST AT EM - ACTIVE SUPPLY CURRENT TEST 26
14
METAL MASK OPTIONS
27
15
28
15
PERIPHERAL MEMORY MAP
28
16
ELECTRICAL SPECIFICATIONS
30
16.1
ABSOLUTE MAXIMUM RATINGS
30
16.2
STANDARD OPERATING CONDITIONS
30
16.3
HANDLING PROCEDURES
30
16.4
DC CHARACTERISTICS - POWER SUPPLY PINS
30
16.5
DC CHARACTERISTICS - INPUT/OUTPUT PINS
31
16.6
DC CHARACTERISTICS - SUPPLY VOLTAGE DETECTOR
LEVELS
32
16.7
OSCILLATOR
33
16.8
INPUT TIMING CHARACTERISTICS
33
17
PAD LOCATION DIAGRAM
34
18
PACKAGE AND ORDERING INFORMATION
34
18.1
ORDERING INFORMATION
36
18.2
PACKAGE MARKING
36
18.3
CUSTOMER MARKING
36
19
SPECIFICATION CHANGE
37
Table of Figures
Figure 1.Architecture
1
Figure 2.Pin Configuration
1
Figure 3.Typical Configuration
4
Figure 4.Mode Transition diagram
5
Figure 5.System reset generation
6
Figure 6.Port A
10
Figure 7.Port B
11
Figure 8.Port C
13
Figure 9.Port D
14
Figure 10.Timer / Event Counter
16
Figure 11.Interrupt Request generation
19
Figure 12.Serial write buffer
22
Figure 13.Automatic Serial Write Buffer transmission
23
Figure 14.Interactive Serial Write Buffer transmission
25
Figure 15. EM6603 PAD Location Diagram
34
Figure 16. Dimensions of PDIP24 Pack. - Pack. type “A”
34
Figure 17. Dimensions of TSSOP24 Pack. - Pack. type “F”
35
Figure 18. Dimensions of SOP24 Pack. SOIC – Pack. type “B”
35
Table of Tables
Table 1. Pin Description
4
Table 2.StandBy and Sleep Activities
5
Table 3. PortA Inputs RESET options (metal Hardware option)
7
Table 4. Watchdog-Timer Option (software option)
7
Table 5. Initial Value After RESET
7
Table 6.Prescaler interrupt source
8
Table 7. Prescaler control register - PRESC
8
Table 8.Watchdog register - WD
8
Table 9.Input / Output Ports Overview
9
Table 10.Option register - Option
9
Table 11.PortA input status register - PortA
10
Table 12.PortA Interrupt request register - IRQpA
10
Table 13.PortA interrupt mask register - MportA
10
Table 14.PortB input status register - PortB
11
Table 15.PortB Input/Output control register - CIOportB
11
Table 16.Ports A&C Interrupt Request
12
Table 17.PortC input/output register - PortC
12
Table 18.PortC Interrupt request register - IRQpC
12
Table 19.PortC interrupt mask register - MportC
12
Table 20.PortD Input/Output register - PortD
14
Table 21.Ports control register - CPIOB
14
Table 22.Buzzer frequency selection
15
Table 23.Buzzer control register - BEEP
15
Table 24.Timer Clock Selection
17
Table 25.Timer control register - TimCtr
17
Table 26.LOW Timer Load/Status register -LTimLS (4 low bits)
17
Table 27.HIGH Timer Load/Status register-HTimLS (4 high bits)
17
Table 28.PA3 counter input selection register - PA3cnt
17
Table 29.PA3 counter input selection
17
Table 30.Main Interrupt request register - IntRq (Read Only)*
18
Table 31.register - CIRQD
19
Table 32. SVLD level selection
20
Table 33.SVLD control register - SVLD
20
Table 34.SWB clock selection
21
Table 35.SWB clock selection register - ClkSWB
21
Table 36.PortD status
21
Table 37.SWB buffer register - SWbuff
22
Table 38.SWB Low size register - LowSWB
22
Table 39.SWB High size register - HighSWB
22
Table 40 Input/Output Ports
27
Table 41 PortA RESET option
27
Table 42 SVLD levels
27
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