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| 型号： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件页数： | 7/69页 |
| 文件大小： | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
15
www.emmicroelectronic.com
6.2.2 Pull-up or Pull-down
Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pull-
down resistor, depending on the selected metal mask options. See the port A metal mask chapter for details.
The pull resistor can be inhibited using the NoPullPA[n] bits in the register OptNoPullPA.
Table 6.2.1. Pull-up or Pull-down Resistor on Port A Inputs
Option mask
pull-up
MPAPU[n]
Option mask
pull-down
MPAPD[n]
NoPullPA[n]
value
Action
no
x
no pull-up, no pull-down
no
yes
0
no pull-up, pull-down
no
yes
1
no pull-up, no pull-down
yes
no
0
pull-up, no pull-down
yes
no
1
no pull-up , no pull-down
yes
x
not allowed*
* only pull-up or pull-down may be chosen on any port A terminal (one choice is excluding the other)
6.2.3 Software Test Variables
The port A terminals PA[2:0] are also used as input conditions for conditional software branches. Independent
of the OPTDebIntPA and the OPTIntEdgPA. These CPU inputs always have a debouncer.
- Debounced PA[0] is connected to CPU TestVar1.
- Debounced PA[1] is connected to CPU TestVar2.
- Debounced PA[2] is connected to CPU TestVar3.
6.2.4 Port A for 10-Bit Counter and MSC
The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode.
As for the IRQ generation one can choose debouncer or direct input with the register OPTDebIntPA and non-
inverted or inverted input with the register OPTIntEdgPA. Debouncer input is always recommended.
Pad input PA[3] is also used as start/stop control for the millisecond counter. This control signal is derived from
PA[3], it is independent of the port A debouncer and edge selection. Refer also to Figure 10.
6.3 Port A Registers
Table 6.3.1 Register RegPA
Bit
Name
Reset
R/W
Description
3
PAData[3]
-
R*
PA[3] input status
2
PAData[2]
-
R*
PA[2] input status
1
PAData[1]
-
R*
PA[1] input status
0
PAData[0]
-
R*
PA[0] input status
* Direct read on port A terminals
with
n=0…3
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