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参数资料
| 型号： | ENC28J60T-I/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET CTRLR W/SPI 28-QFN |
| 标准包装： | 1,600 |
| 控制器类型： | 以太网控制器，MAC/10Base-T |
| 接口： | SPI |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 160mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 配用： | DM163024-ND - BOARD DEMO PICDEM.NET 2 AC164123-ND - BOARD DAUGHTER ETH PICTAIL PLUS AC164121-ND - BOARD DAUGHTER PICTAIL ETHERNET |
2010 Microchip Technology Inc.
DS80349C-page 7
ENC28J60
16. Module: PHY LEDs
With some LEDs, the LED auto-polarity detection
circuit misdetects the connected polarity of the
LED upon Reset. As a result, the LED output pin
will sink current when it should be sourcing current
and vice versa. The LED will visually appear
inverted. For example, an LED configured to dis-
play the link status will be illuminated when no link
is present and extinguished when a link has been
established. The likelihood of a misdetection will
vary over temperature. If LEDB is misdetected, the
PHCON1.PDPXMD bit will also reset to the
incorrect state.
Work around
Place a resistor in parallel with the LED. The
resistor value needed is not critical. Resistors
between 1 k
and 100 k are recommended.
Affected Silicon Revisions
17. Module: DMA
If the DMA module is operated in Checksum mode
(ECON1.CSUMEN, DMAST = 1) at any time while
a packet is currently being received from the
Ethernet (ESTAT.RXBUSY = 1), the packet being
received will be aborted. The packet abort will
cause
the
Receive
Error
Interrupt
Flag
(EIR.RXERIF) to be set, the interrupt will occur, if
enabled, and the Buffer Error status bit
(ESTAT.BUFER) will also become set. The packet
will be permanently lost.
Work around
Do not use the DMA module to perform checksum
calculations; perform checksums in software. This
problem does not affect the DMA copy operation
(ECON1.CSUMEN = 0).
Affected Silicon Revisions
18. Module: Receive Filter
If using the Pattern Match receive filter, some
packets may be accepted that should be
rejected. Specifically, if ERXFCON.ANDOR = 0,
ERXFCON.PMEN = 1 and at least one of the
Hash Table, Magic PacketTM, Broadcast, Multi-
cast or Unicast receive filters are enabled, then
packets can be accepted that do not meet any of
the enabled filter criteria. This will occur if the
receive packet is less than or equal to 64+EPMO
bytes long. For typical applications using the
Pattern Match and Unicast receive filters simul-
taneously with a zero Pattern Match offset, this
will result in the reception of unwanted 64-byte
Address Resolution Protocol (ARP) broadcast
frames, among possible others.
Work around
When using the pattern match receive filter, discard
any unwanted packets in software.
Affected Silicon Revisions
19. Module: SPI Interface
When
operating
in
Power
Save
mode
(ECON2.PWRSV = 1), issuing the SPI System
Reset command will have no effect.
Work around
Clear the PWRSV bit and wait for the device’s
power regulator to stabilize before issuing an SPI
System Reset command.
For a device in an unknown state, the recommended
Reset sequence is:
1. Use the Bit Field Clear command and clear
ECON2.PWRSV (ECON2<5>).
2. Wait at least 300 s for power to be restored.
3. Issue the System Reset command.
4. Wait 1 ms for the Reset to complete and to
ensure that all modules are ready to be used.
5. Confirm that the Reset has taken place. This
can be accomplished by reading a register and
checking for an expected Reset value. For
example, read ESTAT and confirm that the
CLKRDY bit (bit 0) is set and the unimplemented
bit (bit 3) is clear.
If one or both of these conditions are not met,
this may indicate that the ENC28J60 is not
ready yet (e.g., the microcontroller has exited
POR while ENC28J60 is still powering up). In
this case, repeat the procedure from Step 1.
Affected Silicon Revisions
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
B1
B4
B5
B7
XX
X
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