参数资料
型号: EP1C6T256C8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 19/104页
文件大小: 763K
代理商: EP1C6T256C8ES
Altera Corporation
January 2007
2–13
Preliminary
MultiTrack Interconnect
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, PLLs, and M4K memory
blocks within the same row. These row resources include:
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
The direct link interconnect allows an LAB or M4K memory block to
drive into the local interconnect of its left and right neighbors. Only one
side of a PLL block interfaces with direct link and row interconnects. The
direct link interconnect provides fast communication between adjacent
LABs and/or blocks without using row interconnect resources.
The R4 interconnects span four LABs, or two LABs and one M4K RAM
block. These resources are used for fast row connections in a four-LAB
region. Every LAB has its own set of R4 interconnects to drive either left
or right.
Figure 2–9
shows R4 interconnect connections from an LAB. R4
interconnects can drive and be driven by M4K memory blocks, PLLs, and
row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive
a given R4 interconnect. For R4 interconnects that drive to the right, the
primary LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 interconnects for connections from one
row to another.
相关PDF资料
PDF描述
EP1C6T256I6ES Cyclone FPGA Family Data Sheet
EP1C6T256I7ES Cyclone FPGA Family Data Sheet
EP1C6T256I8ES Cyclone FPGA Family Data Sheet
EP1C6T324C6ES Cyclone FPGA Family Data Sheet
EP1C6T324C7ES Cyclone FPGA Family Data Sheet
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