参数资料
型号: EP1C6T256I7ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 96/104页
文件大小: 763K
代理商: EP1C6T256I7ES
4–26
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Tables 4–46
through
4–47
show the adder delays for the IOE
programmable delays. These delays are controlled with the Quartus II
software options listed in the Parameter column.
SSTL-3 class I
1,390
1,598
1,807
ps
SSTL-3 class II
989
1,137
1,285
ps
SSTL-2 class I
1,965
2,259
2,554
ps
SSTL-2 class II
1,692
1,945
2,199
ps
LVDS
802
922
1,042
ps
Note to
Tables 4–40
through
4–45
:
(1)
EP1C3 devices do not support the PCI I/O standard.
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Table 4–46. Cyclone IOE Programmable Delays on Column Pins
Parameter
Setting
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
Off
155
178
201
ps
Small
2,122
2,543
2,875
ps
Medium
2,639
3,034
3,430
ps
Large
3,057
3,515
3,974
ps
On
155
178
201
ps
Decrease input delay to
input register
Off
0
0
0
ps
On
3,057
3,515
3,974
ps
Increase delay to output
pin
Off
0
0
0
ps
On
552
634
717
ps
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