参数资料
型号: EP1K100FC484-2
厂商: Altera
文件页数: 28/86页
文件大小: 0K
描述: IC ACEX 1K FPGA 100K 484-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 60
系列: ACEX-1K®
LAB/CLB数: 624
逻辑元件/单元数: 4992
RAM 位总计: 49152
输入/输出数: 333
门数: 257000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FBGA(23x23)
其它名称: 544-1061
34
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column channels via a multiplexer. The set of column channels is different
for each IOE (see Figure 17).
Figure 17. ACEX 1K Column-to-IOE Connections
Note:
(1)
The values for m and n are shown in Table 9.
Table 9 lists the ACEX 1K column-to-IOE interconnect resources.
Table 9. ACEX 1K Column-to-IOE Interconnect Resources
Device
Channels per Column (n)
Column Channels per Pin (m)
EP1K10
24
16
EP1K30
24
16
EP1K50
24
16
EP1K100
24
16
Each IOE is driven by
a m-to-1 multiplexer
Each IOE can drive two
column channels.
Column
Interconnect
n
m
n
IOE1
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