参数资料
| 型号： | EP1K50FC256-1N |
| 厂商： | Altera |
| 文件页数： | 11/86页 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 256-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 90 |
| 系列： | ACEX-1K® |
| LAB/CLB数： | 360 |
| 逻辑元件/单元数： | 2880 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 186 |
| 门数： | 199000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FBGA（17x17） |
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Altera Corporation
19
ACEX 1K Programmable Logic Device Family Data Sheet
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13
To
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Cascade Chain
With the cascade chain, the ACEX 1K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. With a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EP1K50 device, the cascade
chain stops at the eighteenth LAB, and a new one begins at the nineteenth
LAB). This break is due to the EAB’s placement in the middle of the row.
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is 1.3 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, decoding a 16-bit address
requires 3.1 ns.
Figure 10. ACEX 1K Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n – 1)..(4n – 4)]
d[3..0]
d[7..4]
LE
n
LE1
LE2
LE
n
LUT
AND Cascade Chain
OR Cascade Chain
d[(4
n – 1)..(4n – 4)]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FC256-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC256-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC256-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FC256-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC256-2F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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