参数资料
| 型号： | EP1K50FC484-2 |
| 厂商： | Altera |
| 文件页数： | 86/86页 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 484-FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 60 |
| 系列： | ACEX-1K® |
| LAB/CLB数： | 360 |
| 逻辑元件/单元数： | 2880 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 249 |
| 门数： | 199000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-FBGA（23x23） |
| 其它名称： | 544-1070 |
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Altera Corporation
9
ACEX 1K Programmable Logic Device Family Data Sheet
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Embedded Array Block
The EAB is a flexible block of RAM, with registers on the input and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic functions are implemented by programming the EAB with a read-
only pattern during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performance advantage that is further enhanced by the fast access
times of EABs. The large capacity of EABs enables designers to implement
complex functions in a single logic level without the routing delays
associated with linked LEs or field-programmable gate array (FPGA)
RAM blocks. For example, a single EAB can implement any function with
8 inputs and 16 outputs. Parameterized functions, such as LPM functions,
can take advantage of the EAB automatically.
The ACEX 1K enhanced EAB supports dual-port RAM. The dual-port
structure is ideal for FIFO buffers with one or two clocks. The ACEX 1K
EAB can also support up to 16-bit-wide RAM blocks. The ACEX 1K EAB
can act in dual-port or single-port mode. When in dual-port mode,
separate clocks may be used for EAB read and write sections, allowing the
EAB to be written and read at different rates. It also has separate
synchronous clock enable signals for the EAB read and write sections,
which allow independent control of these sections.
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous reads or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see Figure 2).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FC484-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-2F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FC484-2P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-2X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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