参数资料
型号: EP1K50FC484-3
厂商: Altera
文件页数: 47/86页
文件大小: 0K
描述: IC ACEX 1K FPGA 50K 484-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 60
系列: ACEX-1K®
LAB/CLB数: 360
逻辑元件/单元数: 2880
RAM 位总计: 40960
输入/输出数: 249
门数: 199000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FBGA(23x23)
其它名称: 544-1071
Altera Corporation
51
ACEX 1K Programmable Logic Device Family Data Sheet
D
e
ve
lo
pm
e
n
t
13
To
o
ls
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the ACEX 1K device.
Figure 24. ACEX 1K Device Timing Model
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Figure 25. ACEX 1K Device LE Timing Model
Dedicated
Clock/Input
Interconnect
I/O Element
Logic
Element
Embedded Array
Block
tCGENR
tCO
tCOMB
tSU
tH
tPRE
tCLR
Register
Delays
LUT Delay
tLUT
tRLUT
tCLUT
Carry Chain
Delay
Carry-In
Cascade-In
Data-Out
tCGEN
tCICO
Packed Register
Delay
tPACKED
Register Control
Delay
tC
tEN
Data-In
Control-In
tCASC
Cascade-Out
Carry-Out
tLABCARRY
tLABCASC
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