- 您现在的位置：买卖IC网 > PDF目录299030 > EP1K50FC484 (ALTERA CORP) LOADABLE PLD, PBGA484 PDF资料下载
参数资料
| 型号： | EP1K50FC484 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA484 |
| 封装： | 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484 |
| 文件页数： | 56/84页 |
| 文件大小： | 2224K |
| 代理商： | EP1K50FC484 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页
6
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
f For more information on the configuration of ACEX 1K devices, see the
following documents:
s
Configuration Devices for APEX & FLEX Devices Data Sheet
s
ByteBlasterMV Parallel Port Download Cable Data Sheet
s
BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by the MAX+PLUS II development
system, which is an integrated package that offers schematic, text
(including AHDL), and waveform design entry, compilation and logic
synthesis, full simulation and worst-case timing analysis, and device
configuration. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0,
LPM, VHDL, Verilog HDL, and other interfaces for additional design
entry and simulation support from other industry-standard PC- and
UNIX workstation-based EDA tools.
The MAX+PLUS II software works easily with common gate array EDA
tools for synthesis and simulation. For example, the MAX+PLUS II
software can generate Verilog HDL files for simulation with tools such as
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains
EDA libraries that use device-specific features such as carry chains, which
are used for fast counter and arithmetic functions. For instance, the
Synopsys Design Compiler library supplied with the MAX+PLUS II
development system includes DesignWare functions that are optimized
for the ACEX 1K device architecture.
The MAX+PLUS II development system runs on Windows-based PCs
and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations.
f For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet.
Functional
Description
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
相关PDF资料 |
PDF描述 |
|---|---|
| EP1K50FI256 | LOADABLE PLD, PBGA256 |
| EP1K50FI484 | LOADABLE PLD, PBGA484 |
| EP1K50QC208 | LOADABLE PLD, PQFP208 |
| EP1K50QI208 | LOADABLE PLD, PQFP208 |
| EP1K50TC144 | LOADABLE PLD, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50FC484-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FC484-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FC484-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
发布紧急采购，3分钟左右您将得到回复。