
Altera Corporation
7–1
September 2004
7. Implementing High
Performance DSP Functions
in Stratix & Stratix GX Devices
Introduction
Digital signal processing (DSP) is a rapidly advancing field. With
products increasing in complexity, designers face the challenge of
selecting a solution with both flexibility and high performance that can
meet fast time-to-market requirements. DSP processors offer flexibility,
but they lack real-time performance, while application-specific standard
products (ASSPs) and application-specific integrated circuits (ASICs)
offer performance, but they are inflexible. Only programmable logic
devices (PLDs) offer both flexibility and high performance to meet
advanced design challenges.
The mathematical theory underlying basic DSP building blocks—such as
the finite impulse response (FIR) filter, infinite impulse response (IIR)
filter, fast fourier transform (FFT), and direct cosine transform (DCT)—is
computationally intensive. Altera Stratix and Stratix GX devices
feature dedicated DSP blocks optimized for implementing arithmetic
operations, such as multiply, multiply-add, and multiply-accumulate.
In addition to DSP blocks, Stratix and Stratix GX devices have
TriMatrix embedded memory blocks that feature various sizes that can
be used for data buffering, which is important for most DSP applications.
These dedicated hardware features make Stratix and Stratix GX devices
an ideal DSP solution.
This chapter describes the implementation of high performance DSP
functions, including filters, transforms, and arithmetic functions, using
Stratix and Stratix GX DSP blocks. The following topics are discussed:
■
FIR filters
■
IIR filters
■
Matrix manipulation
■
Discrete Cosine Transform
■
Arithmetic functions
Stratix &
Stratix GX DSP
Block Overview
Stratix and Stratix GX devices feature DSP blocks that can efficiently
implement DSP functions, including multiply, multiply-add, and
multiply-accumulate. The DSP blocks also have three built-in registers
sets: the input registers, the pipeline registers at the multiplier output,
and the output registers.
Figure 7–1 shows the DSP block operating in the
18
× 18-bit mode.
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