Altera Corporation
1
APEX 20K
Programmable Logic
Device Family
August 1999, ver. 2.01
Data Sheet
A-DS-APEX20K-02.01
Features...
s
Industry’s first programmable logic device (PLD) incorporating
System-on-a-Programmable-ChipTM integration
–
MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
–
Embedded system block (ESB) implementation of product-term
logic used for combinatorial-intensive functions
Preliminary
Information
–
LUT logic used for register-intensive functions
–
ESB used to implement memory functions, including first-in
first-out (FIFO) buffers, dual-port RAM, and content-
addressable memory (CAM)
s
High density
–
100,000 to 1 million typical gates (see
Table 1)
–
Up to 38,400 logic elements (LEs)
–
Up to 327,680 RAM bits that can be used without reducing
available logic
–
Up to 2,560 product-term-based macrocells
Notes:
(1)
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 48,000
additional gates.
(2)
This information is preliminary.
Table 1. APEX 20K Device Features
Feature
EP20K60E EP20K100E
EP20K100
EP20K160E EP20K200E
EP20K200
EP20K300E EP20K400E
EP20K400
EP20K600E
EP20K1000E EP20K1500E
Maximum
system
gates
162,000 263,000
404,000
526,000
728,000
1,052,000 1,537,000 1,771,520 2,524,416
Typical
gates
60,000
100,000
160,000
200,000
300,000
400,000
600,000
1,000,000 1,500,000
LEs
2,560
4,160
6,400
8,320
11,520
16,640
24,320
38,400
54,720
ESBs
16
26
40
52
72
104
152
160
228
Maximum
RAM bits
32,768
53,248
81,920
106,496
147,456
212,992
311,296
327,680
466,944
Maximum
macrocells
256
416
640
832
1,152
1,664
2,432
2,560
3,648
Maximum
user I/O
pins
204
252
316
382
408
502
624
716
858