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参数资料
型号： EP20K1500E
厂商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可编程逻辑器件系列
文件页数： 51/117页
文件大小： 570K
代理商： EP20K1500E
Altera Corporation
51
APEX 20K Programmable Logic Device Family Data Sheet
Notes to
Table 15
:
(1)
The PLL input frequency range for the EP20K100-1
X
device for 1x multiplication is 25 MHz to 175 MHz.
(2)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4)
The jitter specification is measured under long-term observation.
(5)
If the input clock stability is 100 ps,
t
JITTER
is 250 ps.
Table 16
summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
t
SKEW
Skew delay between related
ClockLock/ClockBoost-generated clocks
Jitter on ClockLock/ClockBoost-generated clock
(5)
Input clock stability (measured between adjacent
clocks)
500
ps
t
JITTER
200
ps
t
INCLKSTB
50
ps
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
Symbol
Parameter
Min
Max
Unit
f
OUT
f
CLK1
Output frequency
25
25
170
170
MHz
MHz
Input clock frequency (ClockBoost clock multiplication
factor equals 1)
f
CLK2
Input clock frequency (ClockBoost clock multiplication
factor equals 2)
16
80
MHz
f
CLK4
Input clock frequency (ClockBoost clock multiplication
factor equals 4)
10
34
MHz
t
OUTDUTY
f
CLKDEV
Duty cycle for ClockLock/ClockBoost-generated clock
40
60
%
Input deviation from user specification in the Quartus II
software (ClockBoost clock multiplication factor equals
one)
(1)
25,000
(2)
PPM
t
R
t
F
t
LOCK
Input rise time
5
5
ns
ns
μs
Input fall time
Time required for ClockLock/ ClockBoost to acquire
lock
(3)
10
t
SKEW
Skew delay between related ClockLock/ ClockBoost-
generated clock
500
500
ps
t
JITTER
t
INCLKSTB
Jitter on ClockLock/ ClockBoost-generated clock
(4)
200
50
ps
ps
Input clock stability (measured between adjacent
clocks)
相关PDF资料
PDF描述
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
EP20K200E Programmable Logic Device Family
EP20K300E Programmable Logic Device Family
EP20K30E Programmable Logic Device Family
相关代理商/技术参数
参数描述
EP20K1500EBC652-1 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1500EBC652-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K1500EBC652-1X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1500EBC652-2 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 3456 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1500EBC652-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
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