参数资料
型号: EP20K200EFI484-3ES
英文描述: FPGA
中文描述: FPGA的
文件页数: 29/114页
文件大小: 1623K
代理商: EP20K200EFI484-3ES
Altera Corporation
21
APEX 20K Programmable Logic Device Family Data Sheet
Figure 9. APEX 20K Interconnect Structure
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack Interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
MegaLAB
I/O
MegaLAB
I/O
MegaLAB
I/O
Column
Interconnect
Column
Interconnect
Row
Interconnect
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EP20K200EFI672-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K200EFI672-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
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EP20K200EFI672-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K200EQC208-1 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 832 Macro 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256